PPC440GX-3RF800C Applied Micro Circuits Corporation, PPC440GX-3RF800C Datasheet - Page 85

• Manufacturer Part Number: PPC440GX-3RF800C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3RF800C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 800MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.6V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: CBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.19 – December 19, 2008
DDR SDRAM MemClkOut0 and Read Clock Delay
In operation, following the receipt of an address and read command from the PPC440GX, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GX using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
AMCC
Data Sheet
DQS
Data
Package pins
PLB Clock
Cycle
Delay
1/4
D
Stage 1
FF,
XL
C
Q
Programmed
Read Clock
FF Timing:
T
T
T
Delay
P
IS
IH
MemClkOut0(0)
= Propagation delay (D to Q or C to Q) =
Read Clock
= Input setup time = 0.2ns
= Input hold time = 0.1ns
D
PLB Clk
Stage 2
FF
C
Q
T
T
T
T
MD
MD
RD
RD
T
440GX – Power PC 440GX Embedded Processor
T
RD
min =
max =
min =
max =
MD
D
Stage 3
FF
567ps
1705ps
-6ps
183ps
C
Q
0.4ns maximum
(SDRAM0_TR1)
Read Select
Mux
ECC
FF: Flip-Flop
XL: Transparent Latch
D
RDSP
FF
C
Q
PLB bus
85