CY7C0831AV-133BBI Cypress Semiconductor Corp, CY7C0831AV-133BBI Datasheet - Page 21

• Manufacturer Part Number: CY7C0831AV-133BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0831AV-133BBI

• Density: 2Mb
• Access Time (max): 4.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 18b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Notes
Document #: 38-06059 Rev. *S
47. CE
48. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
49. If t
CLK
L_PORT
ADDRESS
R/W
L_PORT
DATA
CLK
R_PORT
ADDRESS
R/W
R_PORT
DATA
> minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t
CCS
0
L
L
R
R
= OE = ADS = CNTEN = BE0 – BE1 = LOW; CE
IN
OUT
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t
t
CKHZ
t
CH2
t
t
CH2
CYC2
Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read
t
t
CYC2
CL2
t
SW
t
t
(continued)
SD
SA
t
CL2
D
A
n
n
t
HA
t
1
CCS
t
SA
= CNTRST = MRST = CNT/MSK = HIGH.
t
HW
t
HD
A
n
t
HA
t
CKLZ
t
CYC2
DC
t
CD2
+ t
CD2
) after the rising edge of R_Port's clock.
CY7C0832BV, CY7C0833AV
CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CYC2
CCS
Q
+ t
n
is violated, indeterminate data is Read out.
CD2
) after the rising edge of R_Port's clock. If t
[47, 48, 49]
Page 21 of 28
CCS
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