ACS8510 Semtech, ACS8510 Datasheet - Page 42

• Manufacturer Part Number: ACS8510
• Manufacturer: Semtech

Specifications of ACS8510

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Holdover mode
Holdover mode
Holdover mode
Holdover mode
Holdover mode
The Holdover mode is used when the ACS8510
has been in Locked mode for long enough to
acquire stable frequency data, but the final
selected reference source has become
unavailable and a replacement has not yet been
qualified for selection.
In Holdover mode, the ACS8510 provides the
timing and synchronisation signals to maintain
the Network Element (NE), but they are not
phase locked to any input reference source.
The timing is based on a stored value of the
frequency ratio obtained during the last Locked
mode period.
To allow for further development of the way
the internal algorithm operates, and to allow
for customised switching behaviour, the switch
to and from Holdover state may be controlled
by external software.
The device must be set in either ‘manual’ mode
or ‘automatic’ mode:
1. Register cnfg_mode bit ‘holdover offset en’ set high
(manual mode).
The Holdover frequency is determined by the value in
register cnfg_holdover_offset. This is a 19 bit signed
number, with a LSB resolution of 0.0003 ppm, which gives
an adjustment range of ± 80 ppm. This value can be derived
from a reading of the register sts_curr_inc_offset (addr
0D, 0C and 07) which gives, in the same format, an
indication of the current output frequency deviation, which
would be read when the device is locked. If required, this
value could be read by an external microcontroller and
averaged over the time required. The averaged value could
then be fed to the cnfg_holdover_offset register ready for
setting of the averaged frequency value when the device
enters Holdover mode. The sts_curr_inc_offset value is
internally derived from the Digital Phase Locked Loop
(DPLL) integral path value, which already represents a well
averaged measure of the current frequency, depending on
the loop bandwidth selected.
2. Register cnfg_mode bit ‘holdover offset en’ set low
(automatic mode).
In automatic control, the device can be run in one of two
ways:
2.1 Register cnfg_holdover_offset register 40 bit 7 ‘auto
holdover averaging’ is set high. The value is averaged
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
Semtech Corp.
42
internally over 32 samples at 32 seconds apart, giving the
average frequency over approximatley the last 20 minutes.
The proportional DPLL path is ignored so that recent signal
disturbances do not affect the Holdover frequency value.
If the device has been previously correctly locked, missing
pulses in the input clock stream fed to the SETS IC are
ignored, hence also avoiding any frequency disturbances
to the output frequency value when an input clock source
fails.
2.2 Register cnfg_holdover_offset register 40 bit 7 ‘auto
holdover averaging’ is set low. This simply freezes the DPLL
at the current frequency (as reported by the
sts_curr_inc_offset register). The proportional DPLL path
is ignored so that recent signal disturbances do not affect
the Holdover frequency value.
Automatic control with internal averaging (option
2.1) is the default condition.
If the TCXO frequency is varying due to
temperature fluctuations in the room, then the
instantaneous value can be different from the
average value, and then it may be possible to
exceed the 0.05 ppm limit (depending on how
extreme the temperature flucuations are). It is
advantageous to shield the TCXO to slow down
frequency changes due to drift and external
temperature fluctuations.
The frequency accuracy of Holdover mode has
to meet the ITU-T, ETSI and Telcordia
performance requirements. The performance
of the external oscillator clock is critical in this
mode, although only the frequency stability is
important - the stability of the output clock in
Holdover is directly related to the stability of
the external oscillator.
Pre-Locked(2) mode
Pre-Locked(2) mode
Pre-Locked(2) mode
Pre-Locked(2) mode
Pre-Locked(2) mode
This state is very similar to the Pre-Locked state.
It is entered from the Holdover state when a
reference source has been selected and applied
to the phase locked loop. It is also entered if
the device is operating in Revertive mode and
a higher-priority reference source is restored.
Upon applying a reference source to the phase
locked loop, the ACS8510 will enter the Locked
state in a maximum of 100 seconds, as defined
ACS8510 Rev2.1 SETS
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