ACS8510 Semtech, ACS8510 Datasheet - Page 13

• Manufacturer Part Number: ACS8510
• Manufacturer: Semtech

Specifications of ACS8510

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

PECL and LVDS ports support the spot clock
frequencies listed plus 155.52 MHz and
311.04 MHz. The choice of PECL or LVDS
compatibility
cnfg_differential_inputs register. Unused PECL/
LVDS differential inputs should be fixed with
one input high (VDD) and the other input low
(GND), or set in LVDS mode and left floating, in
which case one input is internally pulled high
and the other low.
An AMI port supports a composite clock,
consisting of a 64 kHz AMI clock with 8 kHz
boundaries marked by deliberate violations of
the AMI coding rules, as specified in ITU
recommendation G.703. Departures from the
nominal pattern are detected within the
Revision 2.00/September 2003
Notes for Table 4.
Notes for Table 4.
Notes for Table 4.
Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot
frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz
(SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH
is selected using the SONSDHB pin. When the SONSDHB pin is High SONET is selected, when the SONSDHB pin is
Low SDH is selected.
Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz.
Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or
PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin.
ADVANCED COMMUNICATIONS
Notes for Table 4.
Notes for Table 4.
DivN examples
DivN examples
DivN examples
DivN examples
DivN examples
To lock to 2.000 MHz.
To lock to 10.000 MHz.
(4) The DivN register is set to F9 Hex (249 decimal).
(1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the
(2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1).
(3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the
(2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(3) The DivN register is set to 4E1 Hex (1249 decimal).
frequency to E1/DS1. (XX = ‘leaky bucket’ ID for this input).
frequency to 6.48 MHz. (XX = ‘leaky bucket’ ID for this input).
is
programmed
Semtech Corp.
via
the
13
ACS8510, and may cause reference-switching
if too frequent. See section DC Characteristics:
AMI Input/Output Port, for more details. If the
AMI port is unused, the pins (I1 and I2) should
be tied to GND and the VAMI+ supply pin (pin
26) disconnected.
Input Wander and Jitter Tolerance
Input Wander and Jitter Tolerance
Input Wander and Jitter Tolerance
Input Wander and Jitter Tolerance
Input Wander and Jitter Tolerance
The ACS8510 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI DS1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pull-
in, hold-in and pull-out ranges are specified for
each input port in Table 5. Minimum jitter
ACS8510 Rev2.1 SETS
www.semtech.com
FINAL