CY7B991-2JCT Cypress Semiconductor Corp, CY7B991-2JCT Datasheet - Page 16

• Manufacturer Part Number: CY7B991-2JCT
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay Programmable PLL Clock Bufferr

Specifications of CY7B991-2JCT

• Number Of Elements: 1
• Supply Current: 85mA
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Output Frequency Range: 3.75 to 80MHz
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Figure 10
of the downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire
delay) necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumu-
lates low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers
in series.
Document Number: 38-07138 Rev. *E
SYSTEM
CLOCK
shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Figure 10. Board-to-Board Clock Distribution
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
REF
L4
L1
L2
L3
Z
0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
Z
Z
Z
0
0
0
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
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