AD8803AR-REEL Analog Devices Inc, AD8803AR-REEL Datasheet - Page 5

• Manufacturer Part Number: AD8803AR-REEL
• Manufacturer: Analog Devices Inc

Specifications of AD8803AR-REEL

• Number Of Channels: 8
• Resolution: 8b
• Conversion Rate: 1.7MSPS
• Interface Type: Serial (3-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Settling Time: 0.6us
• Architecture: R-2R
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±1.5LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: SOIC N
• Lead Free Status / Rohs Status: Not Compliant

REV. A
For example, when V
ing output voltages will be generated for the following codes:
D
255
128
1
0
REFERENCE INPUTS (V
The reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the V
able to establish a user designed full-scale output voltage. The
external reference voltage can be any value between 0 and V
but must not exceed the V
AD8803, which has access to the V
zero-scale output voltage, any voltage can be applied between
0 V and V
V
shown in Figure 3. The input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55
V
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. The DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
DAC OUTPUTS (O1–O8)
The eight DAC outputs present a constant output resistance of
approximately 5 k independent of code setting. The distribu-
tion of R
However, device to device matching is process lot dependent
having a 20% variation. The change in R
has a 500 ppm/ C temperature coefficient. During power shut-
down all eight outputs are open circuited.
REFH
REFL
H
, which is approximately 2 k . When V
, the REFL reference must be able to sink current out of
SHDN
since the DAC design uses fully bidirectional switches as
CLK
SDI
CS
OUT
DD
V
4.98 V
2.50 V
0.02 V
0.00 V
. V
from DAC to DAC typically matches within 1%.
OX
REFL
D
GND
REG
SER
D10
Figure 4. Block Diagram
D9
D8
D7
D0
can be smaller or larger in voltage than
REFH
.
. .
8
ADDR
DEC
EN
(AD8801 ONLY)
DD
= +5 V and V
REFH
Output State
(V
Full-Scale
Half-Scale (Midscale Reset Value)
1 LSB
Zero-Scale
supply voltage. In the case of the
RS
. . .
. . .
. . .
REFH
, V
AD8801/AD8803
D7
D0
D7
D0
REFL
REFL
= +5 V, V
DAC
REG
DAC
REG
#1
#8
R
R
(AD8803 ONLY)
)
which establishes the
REFL
V
. .
. . . .
OUT
REFL
REFH
REFH
= 0 V the follow-
DAC
DAC
DAC
with temperature
1
8
REFL
is greater than
pin is avail-
= 0 V)
V
V
O1
O2
O3
O4
O5
O6
O7
O8
DD
REFH
DD
–5–
DIGITAL INTERFACING
The AD8801/AD8803 contains a standard three-wire serial in-
put control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Fig-
ure 4 block diagram shows more detail of the internal digital cir-
cuitry. When CS is taken active low, the clock can load data into
the serial register on each positive clock edge, see Table II.
CS
1
0
P
NOTE: P = positive edge, X = don’t care.
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.
The target DAC register is loaded with the last eight bits of the se-
rial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. This applies to
digital input pins CS, SDI, RS, SHDN, CLK.
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 V
the part when it is operated at 3 V.
Figure 6. Equivalent ESD Protection Circuit
CLK
X
P
X
Table II. Input Logic Control Truth Table
DD
Figure 5. Equivalent Control Logic
value. This allows 5 V logic to interface directly to
CLK
SDI
CS
Register Activity
No effect.
Shifts Serial Register one bit loading the
next bit in from the SDI pin.
Data is transferred from the serial register
to the decoded DAC register. See Figure 5.
100
DECODE
AD8801/AD8803
REGISTER
ADDR
SERIAL
LOGIC
DAC 1
DAC 2
DAC 8
. .
.