EPM9320RI208-20 Altera, EPM9320RI208-20 Datasheet - Page 18

• Manufacturer Part Number: EPM9320RI208-20
• Manufacturer: Altera

Specifications of EPM9320RI208-20

• Family Name: MAX 9000
• Memory Type: EEPROM
• # Macrocells: 320
• Number Of Usable Gates: 6000
• Frequency (max): 100MHz
• Propagation Delay Time: 23ns
• Number Of Logic Blocks/elements: 20
• # I/os (max): 132
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: RQFP
• Lead Free Status / Rohs Status: Not Compliant

MAX 9000 Programmable Logic Device Family Data Sheet
Output
Configuration
18
The output buffer in each IOC has an adjustable output slew rate that can
be configured for low-noise or high-speed performance. A slower slew
rate reduces board-level noise and adds a nominal timing delay to the
output buffer delay (t
speed-critical outputs in systems that are adequately protected against
noise. Designers can specify the slew rate on a pin-by-pin basis during
design entry or assign a default slew rate to all pins on a global basis. The
slew rate control affects both rising and falling edges of the output signals.
The MAX 9000 device architecture supports the MultiVolt I/O interface
feature, which allows MAX 9000 devices to interface with systems of
differing supply voltages. The 5.0-V devices in all packages can be set for
3.3-V or 5.0-V I/O pin operation. These devices have one set of V
for internal operation and input buffers (VCCINT), and another set for I/O
output drivers (VCCIO).
The VCCINT pins must always be connected to a 5.0-V power supply.
With a 5.0-V V
therefore compatible with 3.3-V and 5.0-V inputs.
Table 6. Peripheral Bus Sources
Peripheral Control
OE0/ENA0
OE1/ENA1
OE2/ENA2
OE3/ENA3
OE4/ENA4
OE5
OE6
OE7/CLR1
CLR0/ENA5
CLK0
CLK1
CLK2
CLK3
Signal
CCINT
Row C
Row B
Row A
Row B
Row A
Row D
Row C
Row B/GOE
Row A/GCLR Row A/GCLR Row A/GCLR Row A/GCLR
GCLK1
GCLK2
Row D
Row C
level, input voltages are at TTL levels and are
OD
EPM9320
EPM9320A
) parameter. The fast slew rate should be used for
Row E
Row E
Row E
Row B
Row A
Row D
Row C
Row B/GOE
GCLK1
GCLK2
Row D
Row C
EPM9400
Source
Row F
Row F
Row E
Row B
Row A
Row D
Row C
Row B/GOE
GCLK1
GCLK2
Row D
Row C
EPM9480
Altera Corporation
Row G
Row F
Row E
Row B
Row A
Row D
Row C
Row B/GOE
GCLK1
GCLK2
Row D
Row C
EPM9560
EPM9560A
CC
pins