PCF8576CH NXP Semiconductors, PCF8576CH Datasheet - Page 25

• Manufacturer Part Number: PCF8576CH
• Manufacturer: NXP Semiconductors

Specifications of PCF8576CH

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 20
• Number Of Segments: 160
• Package Type: LQFP
• Pin Count: 64
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 315KHz
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF8576C_9
Product data sheet
8.1.4 PCF8576C I
8.1.5 Input filter
8.2 I
The PCF8576C acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to V
A0, A1 and A2 are tied to V
devices with a common I
In the power-saving mode it is possible that the PCF8576C is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I
to slow down fast transmitters. Data loss does not occur.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
The least significant bit of the slave address that a PCF8576C responds to is defined by
the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on
the same I
The I
condition (S) from the I
slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge
in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore
the whole I
After acknowledgement, one or more command bytes (m) follow which define the status of
the addressed PCF8576Cs.
The last command byte is tagged with a cleared most significant bit, the continuation bit C.
The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8576C device. The acknowledgement after
each byte is made only by the (A0, A1 and A2) addressed PCF8576C. After the last
display byte, the I
2
2
C-bus slave address, the transferred command data and the hardware subaddress.
•
•
C-bus protocol
Up to 16 PCF8576Cs on the same I
The use of two types of LCD multiplex on the same I
2
2
C-bus protocol is shown in
C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.
SS
2
2
which defines the hardware subaddress 0. In multiple device applications
C-bus which allows:
C-bus transfer.
2
C-bus controller
2
C-bus master issues a STOP condition (P).
2
C-bus master receiver. The only data output from the PCF8576C are
2
C-bus master which is followed by one of the two PCF8576C
Rev. 09 — 9 July 2009
2
C-bus slave address have the same hardware subaddress.
SS
2
C-bus slave receiver. It does not initiate I
or V
Figure
DD
using a binary coding scheme so that no two
2
18. The sequence is initiated with a START
C-bus for very large LCD applications.
Universal LCD driver for low multiplex rates
2
C-bus.
PCF8576C
2
2
C-bus transfers or
C-bus and serves
© NXP B.V. 2009. All rights reserved.
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