AT93C46A-10PI-2.7 Atmel, AT93C46A-10PI-2.7 Datasheet
AT93C46A-10PI-2.7
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AT93C46A-10PI-2.7 Summary of contents
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... The AT93C46A is available in space-saving 8- lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP packages. The AT93C46A is enabled through the Chip Select pin (CS) and accessed via a three- wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output DO pin ...
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... Table 2-2. Pin Capacitance Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (DO) OUT C Input Capacitance (CS, SK, DI) IN Note: This parameter is characterized and is not 100% tested. AT93C46A 2 *NOTICE: Block Diagram MEMORY ARRAY DATA REGISTER MODE DECODE LOGIC CLOCK GENERATOR = 25° ...
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Table 2-3. DC Characteristics Applicable over recommended operating range from: T Symbol Parameter V Supply Voltage CC1 V Supply Voltage CC2 V Supply Voltage CC3 I Supply Current CC I Standby Current SB1 I Standby Current SB2 I Standby Current ...
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... CS to Status Valid High t DF Impedance t Write Cycle Time WP (1) Endurance 5.0V, 25°C Note: 1. This parameter is characterized and is not 100% tested. AT93C46A 4 = −40° 85° Test Condition 4.5V ≤ V ≤ 5.5V CC 2.7V ≤ V ≤ 5.5V CC 1.8V ≤ V ≤ 5.5V CC 4.5V ≤ V ≤ ...
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... Functional Description The AT93C46A is accessed via a simple and versatile three-wire serial communication inter- face. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location. ...
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... EWEN and EWDS instructions and can be executed at any time. 4. Timing Diagrams Figure 4-1. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 4-1. AT93C46A 6 = 5.0V ± 10%. CC µ s (1) Organization Key for Timing Diagrams I The WRAL instruction is CS AT93C46A 0539L–SEEPR–11/07 ...
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Figure 4-2. READ Timing High Impedance (1) Figure 4-3. EWEN Timing Note: 1. Requires a minimum of nine clock cycles. (1) Figure 4-4. EWDS Timing Note: 1. Requires a minimum ...
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... Figure 4-5. WRITE Timing HIGH IMPEDANCE DO ((1)),( (2)) Figure 4-6. WRAL Timing HIGH IMPEDANCE DO Notes: 1. Valid only 4.5V to 5.5V Requires a minimum of nine clock cycles. Figure 4-7. ERASE Timing HIGH IMPEDANCE DO AT93C46A 8 ... ... ... ... N N-1 N BUSY READY ... D0 N BUSY READY STANDBY CHECK STATUS HIGH IMPEDANCE ...
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Figure 4-8. ERAL Timing HIGH IMPEDANCE DO Note: 1. Valid only 4.5V to 5.5V. CC 0539L–SEEPR–11/ STANDBY CHECK STATUS BUSY HIGH IMPEDANCE ...
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... Ordering Information Ordering Code AT93C46A-10PU-2.7 AT93C46A-10PU-1.8 AT93C46A-10SU-2.7 AT93C46A-10SU-1.8 AT93C46A-10TU-2.7 AT93C46A-10TU-1.8 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values page 4 . Not recommended for new design. Please see AT93C46E datasheet. 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" ...
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Packaging Information 5.1 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L ...
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... JEDEC SOIC Top View e Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT93C46A TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...
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TSSOP Pin 1 indicator this corner N Top View Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, ...
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... Revision History Doc. Rev. 0539L 0539K AT93C46A 14 Date Comments 11/2007 Modified ‘max’ values on DC/AC Characteristics tables. Implemented revision history. Added Note to page 1 and ordering information; Not 2/2007 recommended for new design; please refer to AT93C46E datasheet. 0539L–SEEPR–11/07 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...