HN58X2464TI Renesas Electronics America, HN58X2464TI Datasheet - Page 15

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HN58X2464TI

Manufacturer Part Number
HN58X2464TI
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HN58X2464TI

Density
64Kb
Interface Type
Serial (2-Wire)
Organization
8Kx8
Access Time (max)
900ns
Frequency (max)
400KHz
Write Protection
Yes
Data Retention
10Year
Operating Supply Voltage (typ)
2.5/3.3/5V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Supply Current
3mA
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Not Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
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Manufacturer:
HIT
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Part Number:
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Manufacturer:
HITACHI/日立
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Part Number:
HN58X2464TIE
Manufacturer:
RENESAS/瑞萨
Quantity:
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HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to
be written in a single write cycle. The page write is the same sequence as the byte write except for
inputting the more write data. The page write is initiated by a start condition, device address word,
memory address(n) and write data(Dn) with every ninth bit acknowledgment. The EEPROM enters the
page write operation if the EEPROM receives more write data(Dn+1) instead of receiving a stop condition.
The a0 to a4 address bits are automatically incremented upon receiving write data(Dn+1). The EEPROM
can continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the last address of the
page, the a0 to a4 address bits will roll over to the first address of the same page and previous write data
will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
Rev.5.00, Jan.14.2005, page 13 of 20
Notes: 1. Don‘t care bits for 32k and 64k.
8k to
32k to
16k
64k
Start
Start
2. Don‘t care bit for 32k.
1 0 1 0
1 0 1 0
Device
address
Device
address
W
W
R/W
R/W
Memory
address (n)
1st Memory
address (n)
ACK
ACK
Write data (n)
ACK
ACK
2nd Memory
address (n)
ACK
Write data (n+m)
ACK
Write data (n)
Write data (n+m)
ACK
ACK
Stop
ACK
Stop

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