CYNSE70064A-83BGC Cypress Semiconductor Corp, CYNSE70064A-83BGC Datasheet - Page 22

• Manufacturer Part Number: CYNSE70064A-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-83BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

10.4
The Write can be a single Write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst
Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask array locations.
A single-location Write is a 3-cycle operation, as shown in Figure 10-3. The burst Write adds one extra cycle for each successive
location Write..
The following is the Write operation sequence, and Table 10-7 shows the Write address format for the data array, the mask array,
or single-Write SRAM. Table 10-8 shows the Write address format for the internal registers.
At the termination of cycle 3, another operation can begin.
Note. The latency of the SRAM Write will be different than the one described above (see Subsection 12.2, “SRAM PIO Access”
on page 102).
Table 10-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
Table 10-8. Write Address Format for Internal Registers
Document #: 38-02041 Rev. *F
Reserved 0: Direct
Reserved 0: Direct
Reserved 0: Direct
• Cycle 1A: The host ASIC applies the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied
• Cycle 1B:The host ASIC continues to apply the Write instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data array, mask array, or register location of
• Cycle 3: Idle cycle.
[67:30]
on the DQ bus. The host ASIC also supplies the GMR Index to mask the Write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply the SADR[21:20] on CMD[8:7].
address supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the
devices when DQ[25:21] = 11111.
the selected device.
DQ
DQ[67:26]
Reserved
Write Command
1: Indirect
1: Indirect
1: Indirect
DQ[29]
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
cable if DQ[29]
cable if DQ[29]
cable if DQ[29]
SSR (appli-
SSR (appli-
SSR (appli-
DQ
DQ[28:26]
is indirect)
is indirect)
is indirect)
DQ[25:21]
ID
cycle 0
[25:21]
DQ
ID
ID
ID
Figure 10-3. Single Write Cycle Timing
01: Mask Array Reserved If DQ[29] is 0, this field carries the address of the mask
00: Data Array Reserved If DQ[29] is 0, this field carries the address of the data
10: External
DQ[20:19]
A
cycle 1
SRAM
Address
Write
11: Register
DQ[20:19]
B
Reserved If DQ[29] is 0, this field carries the address of the
[18:15]
cycle 2
DQ
Data
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of data array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
array location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of the mask array location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
SRAM location.
If DQ[29] is 1, the SSR specified on DQ[28:26] is used
to generate the address of SRAM location:
{SSR[14:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.
Reserved
DQ[18:6]
cycle 3
X
DQ[14:0]
cycle 4
Register address
CYNSE70064A
DQ[5:0]
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