CYNSE70064A-83BGC Cypress Semiconductor Corp, CYNSE70064A-83BGC Datasheet - Page 21

• Manufacturer Part Number: CYNSE70064A-83BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-83BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The Read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
starting address (ADR) and the length of the transfer (BLEN) before initiating the burst Read command.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG
are complete. On the last transfer, the CYNSE70064A drives the EOT signal HIGH.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to the three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 10-6 describes the Read address format for data and mask arrays for burst
Read operations.
Table 10-6. Read Address Format for Data and Mask Arrays
Document #: 38-02041 Rev. *F
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
• Cycle 2: The host ASIC floats DQ[67:0] to the three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in the three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus and drives ACK and EOT from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
• Cycle (4 + 2n): The selected device drives the DQ[67:0] to the three-state condition, and drives the ACK and EOT signals LOW.
on the DQ bus, as shown in Table 10-6. The host ASIC selects the CYNSE70064A where ID[4:0] matches the DQ[25:21] lines.
If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set.
signal HIGH.
DQ[67:26]
Reserved
Reserved
DQ[25:21]
CMD[8:2]
CMD[1:0]
CMDV
CLK2X
PHS_L
ID
ID
ACK
EOT
DQ
Figure 10-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
Address
cycle
Read
01: Mask Array
A B
00: Data Array
1
DQ[20:19]
cycle
2
cycle
3
cycle
FF
4
cycle
Data0
5
DQ[18:15]
Reserved
Reserved
cycle
6
FF
cycle
Data1
7
cycle
8
FF
Do not care. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
Do not care. These 15 bits come from the internal
register (RBURADR) which increments for each
access.
cycle
Data2
9
cycle
10
FF
cycle
11
Data3
cycle
12
DQ[14:0]
CYNSE70064A
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