CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 48

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Note. For 136-bit searches, the host ASIC must supply two distinct 68-bit data words on DQ[67:0] during cycles A and B. The
even-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle A. The odd-numbered GMR
of the pair specified by the GMR Index is used for masking the word in cycle B.
The logical 136-bit Search operation is shown in Figure 10-29. The entire table of 136-bit entries is compared to a 136-bit word
K (presented on the DQ bus in cycles A and B of the command) using the GMR and the local mask bits. The GMR is the 136-bit
word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A. The 136-bit word K
(presented on the DQ bus in cycles A and B of the command) is also stored in both even and odd comparand register pairs
selected by the Comparand Register Index in the command’s cycle B. The two comparand registers can subsequently be used
by the Learn command with the even comparand register stored in an even location, and the odd comparand register stored in
an adjacent odd location. The word K (presented on the DQ bus in cycles A and B of the command) is compared with each entry
in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the
SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 101). Note. The matching address is always going to
an even address for a 136-bit Search.
The Search command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 136-bit
searches in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search
command cycle (two CLK2X cycles) is shown in Table 10-18.
Table 10-18. The Latency of Search from Instruction to SRAM Access Cycle
For a single device in the table with TLSZ = 00, the latency of the Search from command to SRAM access cycle is 4. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in Table 10-19.
Table 10-19. Shift of SSF and SSV from SADR
Document #: 38-02041 Rev. *F
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
000
001
010
100
101
011
110
111
Comparand Register (odd)
Comparand Register (even)
67
A
B
Figure 10-29.
0
Max Table Size
128K × 136 bits
496K × 136 bits
16K × 136 bits
Location
address
32766
GMR
L
0
2
4
6
×
K
136 Table with One Device
135
135
(136-bit configuration)
Even
CFG = 01010101
A
Number of CLK Cycles
Odd
B
0
0
1
2
3
4
5
6
7
0
(First matching entry)
Latency in CLK Cycles
4
5
6
CYNSE70064A
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