CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 32

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 10-14. Shift of SSF and SSV from SADR (continued)
10.8
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 10-13. Each of the four blocks in the diagram
represents eight CYNSE70064A devices (except the last, which has seven devices). The diagram for a block of eight devices is
shown in Figure 10-14. The following are the parameters programmed into the 31 devices.
Note. All 31 devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 10-15. For the purpose of
illustrating the timings, it is further assumed that the there is only one device with a matching entry in each of the blocks.
Figure 10-15 shows the timing diagram for a Search command in the 68-bit-configured table of 31 devices for each of the eight
devices in block 0. Figure 10-16 shows a timing diagram for a Search command in the 68-bit-configured table of 31 devices for
the all the devices in block number 1 (above the winning device in that block). Figure 10-17 shows the timing diagram for the
globally winning device (defined as the final winner within its own and all blocks) in block number 1. Figure 10-18 shows the timing
diagram for all the devices below the globally winning device in block number 1. Figure 10-19, Figure 10-20, and Figure 10-21
show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below
the globally winning device, respectively, for block number 2. Figure 10-22, Figure 10-23, Figure 10-24, and Figure 10-25 show
the timing diagrams of the devices above globally winning device, the globally winning device, and the devices below the globally
winning device except the last device (device 30), respectively, for block number 3.
The 68-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices
knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block arbitrate
for a winner amongst them (a “block” being defined as less than or equal to eight devices resolving the winner within them using
the LHI[6:0] and LHO[1:0] signalling mechanism). In the sixth cycle after the Search command, the blocks (of devices) resolve
the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the
global winning device for a Search operation.
Table 10-15. Hit/Miss Assumptions
Document #: 38-02041 Rev. *F
• First thirty devices (devices 0–29): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Search Number
68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70064A Devices
Block 0
Block 1
Block 2
Block 3
HLAT
110
111
Miss
Miss
Miss
Hit
1
Miss
Miss
Hit
Hit
2
Number of CLK Cycles
6
7
Miss
Miss
Hit
Hit
3
CYNSE70064A
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Miss
Miss
Miss
Miss
4