CY7C68013-56LFXC Cypress Semiconductor Corp, CY7C68013-56LFXC Datasheet - Page 7

no-image

CY7C68013-56LFXC

Manufacturer Part Number
CY7C68013-56LFXC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C68013-56LFXC

Cpu Family
FX2LP
Device Core
8051
Device Core Size
8b
Frequency (max)
48MHz
Interface Type
USB
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
24
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
56
Package Type
QFN EP
Lead Free Status / Rohs Status
Compliant
3.11
3.12
3.12.1
3.12.2
Bidirectional endpoint zero, 64-byte buffer
64-byte buffers, bulk or interrupt
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2
and 6 can be either double, triple, or quad buffered. For high-
speed endpoint configuration options, see Figure 3-3.
Document #: 38-08012 Rev. *F
• 3 × 64 bytes
• 8 × 512 bytes
• EP0
• EP1IN, EP1OUT
• EP2,4,6,8
Register Addresses
Endpoint RAM
Size
Organization
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
FFFF
EFFF
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E600
E5FF
E480
E47F
E400
E3FF
E200
E1FF
F000
E000
128 bytes GPIF Waveforms
384 bytes RESERVED
4 kbytes EP2-EP8 buffers
64 bytes RESERVED
256 bytes Registers
64 bytes EP0 IN/OUT
512 bytes RESERVED
64 bytes EP1OUT
2 kbytes RESERVED
64 bytes EP1IN
8051 xdata RAM
3.12.3
A separate eight-byte buffer at 0xE6B8-0xE6BF holds the
SETUP data from a CONTROL transfer.
3.12.4
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. To the left of the vertical line,
the user may pick different configurations for EP2&4 and
EP6&8, since none of the 512-byte buffers are combined
between these endpoint groups. An example endpoint config-
uration would be:
EP2—1024 double buffered; EP6—512 quad buffered.
To the right of the vertical line, buffers are shared between
EP2–8, and therefore only entire columns may be chosen.
(8 × 512)
512 bytes
Set-up Data Buffer
Endpoint Configuration (High-speed Mode)
CY7C68013
Page 7 of 48

Related parts for CY7C68013-56LFXC