CY7C68013-56LFXC Cypress Semiconductor Corp, CY7C68013-56LFXC Datasheet - Page 18

• Manufacturer Part Number: CY7C68013-56LFXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFXC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Compliant

Table 4-1. FX2 Pin Descriptions (continued)
Document #: 38-08012 Rev. *F
TQFP
Port B
PORT C
128
92
44
45
46
47
54
55
56
57
72
73
74
75
76
TQFP
100
74
34
35
36
37
44
45
46
47
57
58
59
60
61
SSOP
56
47
25
26
27
28
29
30
31
32
QFN
56
40 PA7 or
18 PB0 or
19 PB1 or
20 PB2 or
21 PB3 or
22 PB4 or
23 PB5 or
24 PB6 or
25 PB7 or
FLAGD or
SLCS#
FD[0]
FD[1]
FD[2]
TXD1 or
FD[3]
FD[4]
FD[5]
FD[6]
FD[7]
PC0 or
GPIFADR0
PC1 or
GPIFADR1
PC2 or
GPIFADR2
PC3 or
GPIFADR3
PC4 or
GPIFADR4
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
[5]
Default
(PC0)
(PC1)
(PC2)
(PC3)
(PC4)
(PA7)
(PB0)
(PB1)
(PB2)
(PB3)
(PB4)
(PB5)
(PB6)
(PB7)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Description
CY7C68013
Page 18 of 48