CY7C68013-128AXC Cypress Semiconductor Corp, CY7C68013-128AXC Datasheet - Page 42

• Manufacturer Part Number: CY7C68013-128AXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AXC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Compliant

9.16.3
Figure 9-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
Document #: 38-08012 Rev. *F
FLAGS
FIFOADR
FIFO DATA BUS Not Driven
FIFO POINTER
• At t = 0 the FIFO address is stable and the SLCS signal is
• At t = 1, SLOE is asserted. This results in the data bus being
• At t = 2, SLRD is asserted. The SLRD must meet the
SLRD
SLCS
DATA
SLOE
asserted.
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
minimum active pulse of t
pulse width of t
in asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition).
Sequence Diagram of a Single and Burst Asynchronous Read
t=0
t=1
RDpwh
N
Driven
Data (X)
t
Figure 9-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SFA
t
OEon
SLOE
Figure 9-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
. If SLCS is used then, SLCS must be
t=2
t
RDpwl
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
and minimum de-active
t
FAH
SLRD
t
t
OEoff
XFLG
N
N
SLRD
T=0
N+1
T=1
N
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
t
N+1
RDpwl
t
XFD
T=3
SLOE
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
• The data that will be driven, after asserting SLRD, is the
t
N+1
RDpwh
updated data from the FIFO. This data is valid after a propa-
gation delay of t
Figure 9-19, data N is the first valid data read from the FIFO.
For data to appear on the data bus during the read cycle
(i.e., SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
N+1
N
T=4
SLRD
t
RDpwl
t
XFD
N+1
T=5
N+1
SLRD
t
N+2
RDpwh
XFD
N+2
T=6
N+1
from the activating edge of SLRD. In
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
t
OEoff
t
XFLG
N+3
N+2
CY7C68013
Page 42 of 48
SLOE
Not Driven
N+3