CY7C68013-128AC Cypress Semiconductor Corp, CY7C68013-128AC Datasheet - Page 35

• Manufacturer Part Number: CY7C68013-128AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

9.7
Table 9-7. Slave FIFO Asynchronous Read Parameters
9.8
Table 9-8. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Document #: 38-08012 Rev. *F
t
t
t
t
t
t
t
t
t
t
t
t
Note:
16. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
RDpwl
RDpwh
XFLG
XFD
OEon
OEoff
IFCLK
SWR
WRH
SFD
FDH
XFLG
Parameter
Parameter
Slave FIFO Asynchronous Read
Slave FIFO Synchronous Write
SLRD Pulse Width LOW
SLRD Pulse Width HIGH
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
IFCLK Period
SLWR to Clock Set-up Time
Clock to SLWR Hold Time
FIFO Data to Clock Set-up Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
FLAGS
FLAGS
DATA
SLOE
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram
IFCLK
SLRD
SLWR
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram
DATA
Z
Description
Description
t
OEon
N
t
[16]
RDpwl
t
XFD
t
SWR
t
SFD
N+1
t
IFCLK
t
WRH
t
N
t
XFLG
FDH
t
XFLG
t
t
RDpwh
OEoff
20.83
Min.
Min.
18.1
9.2
50
50
0
0
Z
[15]
[13]
[13]
Max.
Max.
10.5
10.5
9.5
70
15
CY7C68013
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Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns