CY7C68013-128AC Cypress Semiconductor Corp, CY7C68013-128AC Datasheet - Page 26

• Manufacturer Part Number: CY7C68013-128AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Table 5-1. FX2 Register Summary (continued)
Document #: 38-08012 Rev. *F
E6AE
E6CF
E6AF
E6B0
E6B1
E6B2
E6B3
E6B4
E6B5
E6B8
E6C0
E6C1
E6C2
E6C3
E6C4
E6C5
E6C6
E6C7
E6C8
E6C9
E6D0
E6D1
E6D2
E6D3
E6D4
Hex Size Name
E6A
E6A
E6C
E6C
E6C
E6C
E6C
E6D
E6D
E6D
C
D
A
B
C
D
E
A
B
C
1
1
1
1
1
1
1
1
1
1
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
3
1
1
1
3
EP2FIFOBCL
EP4FIFOBCH
EP4FIFOBCL
EP6FIFOBCH
EP6FIFOBCL
EP8FIFOBCH
EP8FIFOBCL
SUDPTRH
SUDPTRL
SUDPTRCTL
reserved
SETUPDAT
GPIF
GPIFWFSELECT Waveform Selector
GPIFIDLECS
GPIFIDLECTL
GPIFCTLCFG
GPIFADRH
GPIFADRL
FLOWSTATE
FLOWSTATE
FLOWLOGIC
FLOWEQ0CTL
FLOWEQ1CTL
FLOWHOLDOFF Holdoff Configuration
FLOWSTB
FLOWSTBEDGE Flowstate Rising/Falling
FLOWSTBPERI-
OD
GPIFTCB3
GPIFTCB2
GPIFTCB1
GPIFTCB0
reserved
reserved
reserved
EP2GPIFFLGSEL
[6]
EP2GPIFPFSTOP Endpoint 2 GPIF stop trans-
EP2GPIFTRIG
reserved
reserved
reserved
EP4GPIFFLGSEL
[6]
EP4GPIFPFSTOP Endpoint 4 GPIF stop trans-
EP4GPIFTRIG
reserved
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
Description
Endpoint 2 slave FIFO total
byte count L
Endpoint 4 slave FIFO total
byte count H
Endpoint 4 slave FIFO total
byte count L
Endpoint 6 slave FIFO total
byte count H
Endpoint 6 slave FIFO total
byte count L
Endpoint 8 slave FIFO total
byte count H
Endpoint 8 slave FIFO total
byte count L
Setup Data Pointer high ad-
dress byte
Setup Data Pointer low ad-
dress byte
Setup Data Pointer Auto
Mode
8 bytes of SETUP data
SETUPDAT[0] =
SETUPDAT[1] = bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] = wLength
GPIF Done, GPIF IDLE drive
mode
Inactive Bus, CTL states
CTL Drive Type
GPIF Address H
GPIF Address L
Flowstate Enable and Selec-
tor
Flowstate Logic
CTL-Pin States in Flowstate
(when Logic = 0)
CTL-Pin States in Flowstate
(when Logic = 1)
Flowstate Strobe Configura-
tion
Edge Configuration
Master-Strobe Half-Period
GPIF Transaction Count
Byte 3
GPIF Transaction Count
Byte 2
GPIF Transaction Count
Byte 1
GPIF Transaction Count
Byte 0
Endpoint 2 GPIF Flag select
action on prog. flag
Endpoint 2 GPIF Trigger
Endpoint 4 GPIF Flag select
action on GPIF Flag
Endpoint 4 GPIF Trigger
bmRequestType
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE
LFUNC1
CTL0E3
CTL0E3
TRICTL
GPIFA7
SLAVE
DONE
TC31
TC23
TC15
BC7
BC7
BC7
BC7
FSE
TC7
A15
D7
D7
b7
A7
0
0
0
0
0
0
0
0
0
0
0
x
x
RDYASYNC
LFUNC0
CTL0E2
CTL0E2
GPIFA6
TC30
TC22
TC14
BC6
BC6
BC6
BC6
TC6
A14
D6
D6
b6
A6
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
x
CTLTOGL
TERMA2
CTL0E1/
CTL0E1/
GPIFA5
CTL5
CTL5
CTL5
CTL5
TC29
TC21
TC13
BC5
BC5
BC5
BC5
TC5
A13
D5
D5
b5
A5
0
0
0
0
0
0
0
0
0
0
x
0
0
x
SUSTAIN
TERMA1
CTL0E0/
CTL0E0/
GPIFA4
CTL4
CTL4
CTL4
CTL4
TC28
TC20
TC12
BC4
BC4
BC4
BC4
A12
TC4
A4
D4
D4
b4
0
0
0
0
0
0
0
0
0
0
x
0
0
x
TERMA0
GPIFA3
BC11
CTL3
CTL3
CTL3
CTL3
TC27
TC19
TC11
BC3
BC3
BC3
BC3
TC3
A11
D3
D3
b3
A3
0
0
0
0
0
0
0
0
0
0
x
0
0
x
FIFOWR0
TERMB2
HOCTL2
GPIFA2
MSTB2
BC10
BC10
BC10
CTL2
CTL2
CTL2
CTL2
TC26
TC18
TC10
BC2
BC2
BC2
BC2
FS2
TC2
A10
D2
D2
b2
A2
0
0
0
0
0
0
x
0
0
x
FIFORD1
TERMB1
FALLING
HOCTL1
GPIFA1
MSTB1
CTL1
CTL1
CTL1
CTL1
TC25
TC17
BC1
BC9
BC1
BC9
BC1
BC9
BC1
TC9
TC1
FS1
FS1
FS1
b1
A9
A1
D1
D1
0
0
0
0
0
x
x
FIFO2FLAG 00000000
FIFO4FLAG 00000000
SDPAUTO 00000001
FIFORD0
IDLEDRV
TERMB0
HOCTL0
GPIFA8
GPIFA0
RISING
MSTB0
CY7C68013
CTL0
CTL0
CTL0
CTL0
TC24
TC16
BC0
BC8
BC0
BC8
BC0
BC8
BC0
FS0
TC8
TC0
FS0
FS0
A8
D0
D0
b0
0
x
x
Page 26 of 48
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10000000
00000000
00000000
00000000
00000000 brrrrbbb
00000000
00000000
00000000
00010010
00100000
00000001
00000010
00000000
00000000
00000000
00000001
00000000
00000000
00000000
11100100
xxxxxxxx
xxxxxxx0 bbbbbbbr
xxxxxxxx
11111111
xxxxxxxx
xxxxxxxx
Default
Access
rrrrrrbb
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
R
R
R
R
R
R