CY7C346B-25NC Cypress Semiconductor Corp, CY7C346B-25NC Datasheet - Page 4

• Manufacturer Part Number: CY7C346B-25NC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C346B-25NC

• Family Name: MAX®
• Memory Type: EPROM
• # Macrocells: 128
• Number Of Usable Gates: 2500
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 8
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03037 Rev. *C
Logic Array Blocks
There are eight logic array blocks in the CY7C346B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macro-
cells in other LABs as well as the macrocells in the LAB in
which they are situated.
Design Recommendations
Operation of the devices described herein with conditions
above those listed in the “Maximum Ratings” section of this
datasheet may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure
to absolute maximum ratings conditions for extended periods
of time may affect device reliability. The CY7C346B contains
circuitry to protect device pins from high static voltages or
electric fields, but normal precautions should be taken to avoid
application of any voltage higher than the maximum rated
voltages.
For proper operation, input and output pins must be
constrained to the range GND ≤ (V
inputs must always be tied to an appropriate logic level
(either V
INPUT
CC
or GND). Each set of V
DELAY
DELAY
INPUT
PIA
t
t
PIA
IN
IN
or V
CC
SYSTEM CLOCK DELAY t
and GND pins must
Figure 1. CY7C346B Internal Timing Model
OUT
USE ULTRA37000™ FOR
CONTROL DELAY
LOGIC ARRAY
LOGIC ARRAY
) ≤ V
EXPANDER
ALL NEW DESIGNS
DELAY
CLOCK
DELAY
DELAY
t
t
t
CC
LAD
LAC
EXP
I/O DELAY
t
IC
. Unused
t
IO
t
t
t
t
CLR
PRE
RSU
RH
ICS
FEEDBACK
Externally, the CY7C346B provides 20 dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
be connected directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between V
each V
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
Design Security
The CY7C346B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
DELAY
t
FD
REGISTER
CC
t
t
LATCH
COMB
t
RD
CC
pin should be separately decoupled to GND
and GND. For the most effective decoupling,
OUTPUT
DELAY
t
t
t
OD
XZ
ZX
CY7C346B
C346B–9
Page 4 of 15
OUTPUT