CY7C274-30WC Cypress Semiconductor Corp, CY7C274-30WC Datasheet
CY7C274-30WC
Manufacturer Part Number
CY7C274-30WC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheets
1.CY7C274-30WC.pdf
(11 pages)
2.CY7C274-30WC.pdf
(11 pages)
3.CY7C274-30WC.pdf
(11 pages)
Specifications of CY7C274-30WC
Density
256Kb
Access Time (max)
30ns
Supply Current
120mA
Pin Count
28
Mounting
Through Hole
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C274-30WC
Manufacturer:
CYPRESS
Quantity:
1 000
Features
Functional Description
The
32,768-word by 8-bit CMOS PROMs. When disabled (CE
HIGH), the 7C271/7C274 automatically powers down into a
Cypress Semiconductor Corporation
Document #: 38-04008 Rev. *B
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
• Low power
• Super low standby power
• EPROM technology 100% programmable
• Slim 300-mil package (7C271)
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
Logic Block Diagram
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
— 30 ns (Commercial)
— 35 ns (Military)
— 660 mW (commercial)
— 715 mW (military)
— Less than 165 mW when deselected
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
(7C271) CS
(7C271) CS
CY7C271
(7C274) OE
CE
X ADDRESS
1
2
Y ADDRESS
and
PROGRAMABLE
256 x 1024
ARRAY
CY7C274
POWER-DOWN
MULTIPLEXER
8 x 1 OF 128
are
•
high-performance
3901 North First Street
Pin Configurations
low-power stand-by mode. The CY7C271 is packaged in the
300-mil slim package. The CY7C274 is packaged in the
industry standard 600-mil package. Both the CY7C271 and
CY7C274 are available in a cerDIP package equipped with an
erasure window to provide for reprogrammability. When
exposed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM floating
gate technology and byte-wide intelligent programming
algorithms.
The CY7C271 and CY7C274 offer the advantage of lower
power, superior performance, and programming yield. The
EPROM cell requires only 12.5V for the super voltage, and low
current requirements allow for gang programming. The
EPROM cells allow each memory location to be tested 100%
because each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming, the product will meet DC and AC specification
limits.
Reading the 7C271 is accomplished by placing active LOW
signals on CS
7C274 is accomplished by placing active LOW signals on OE and
CE. The contents of the memory location addressed by the address
lines (A
O
O
O
O
O
O
O
O
7
6
5
4
3
2
1
0
32K x 8 Power Switched and
0
NC
O
A
A
A
A
A
•
A
A
LCC/PLCC (Opaque Only)
6
3
2
1
0
5
4
0
A
GND
14
O
O
O
A
A
A
A
A
A
A
A
A
A
5
6
7
8
9
10
11
12
13
San Jose
9
8
7
5
4
1
0
0
1
2
6
3
2
Reprogrammable PROM
) will become available on the output lines (O
14151617
4
1
DIP/Flatpack
and CE, and an active HIGH on CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3 2 1
7C271
7C271
32
181920
31
28
27
26
25
24
23
22
21
20
19
18
17
16
15
30
•
29
28
27
26
25
24
23
22
21
CS
CS
V
A
A
A
A
A
CE
O
O
O
O
O
CC
10
11
12
13
14
7
6
5
4
3
1
2
CA 95134
A
A
A
NC
CS
CS
CE
O
O
12
13
14
7
6
1
2
Revised December 27, 2002
LCC/PLCC (Opaque Only)
NC
O
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
GND
V
A
O
O
O
A
A
A
A
A
A
A
A
PP
12
5
6
7
8
9
10
11
12
13
7
6
5
4
3
2
1
0
0
1
2
14151617
4
•
DIP/Flatpack
1
2
3
4
5
6
7
8
9
10
11
12
13
14
3 2 1
7C274
7C274
408-943-2600
CY7C271
CY7C274
2
32
. Reading the
181920
31
28
27
26
25
24
23
22
21
20
19
18
17
16
15
30
0
29
28
27
26
25
24
23
22
21
O
V
A
A
A
A
A
OE
A
CE
O
O
O
O
O
CC
14
13
8
9
11
10
7
6
5
4
3
7
A
A
A
NC
OE
A
CE
O
O
).
8
9
11
10
7
6
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