CY7C1355B-133AC Cypress Semiconductor Corp, CY7C1355B-133AC Datasheet - Page 13

• Manufacturer Part Number: CY7C1355B-133AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355B-133AC

• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05117 Rev. *C
.
Interleaved Burst Address Table
(MODE = Floating or V
ZZ Mode Electrical Characteristics
.
Truth Table
I
t
t
t
t
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK
EDGE (Stall)
Sleep MODE
Notes:
DDZZ
ZZS
ZZREC
ZZI
RZZI
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
3. Write is defined by BW
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQs and DQP
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
Address
Parameter
Selects are asserted, see Truth Table for details.
OE is inactive or when the device is deselected, and DQs and DQP
A1: A0
First
00
01
10
11
Operation
[2, 3, 4, 5, 6, 7, 8]
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
X
Address
Second
A1: A0
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
01
00
11
10
, and WE. See Truth Table for Read/Write.
DD
Address
External
External
External
Current
Used
None
None
None
None
None
None
)
Next
Next
Next
Next
Address
Description
A1: A0
Third
10
00
01
11
CE
H
X
X
X
X
X
X
X
X
X
L
L
L
L
1
CE
X
X
X
H
X
H
X
H
X
H
X
X
X
L
Address
Fourth
A1: A0
2
11
10
01
00
CE
X
H
X
X
X
X
X
X
X
X
L
L
L
L
X
3
= data when OE is active.
ZZ ADV/LD
H
L
L
L
L
L
L
L
L
L
L
L
L
L
ZZ > V
ZZ < 0.2V
ZZ > V
This parameter is sampled
This parameter is sampled
Linear Burst Address Table
(MODE = GND)
H
H
H
H
H
X
X
L
L
L
L
L
L
L
Address
Test Conditions
A1: A0
DD
DD
First
00
01
10
11
– 0.2V
– 0.2V
WE
H
H
X
X
X
X
X
X
L
X
X
X
X
L
Address
Second
BW
A1: A0
X
X
X
X
X
X
X
X
H
H
X
X
L
L
01
10
11
00
X
OE
X
X
X
X
H
H
X
X
X
X
X
X
L
L
2t
Min.
CYC
0
Address
CEN CLK
A1: A0
Third
H
X
L
L
L
L
L
L
L
L
L
L
L
L
10
00
01
11
CY7C1355B
CY7C1357B
L->H Three-State
L->H Three-State
L->H Three-State
L->H Three-State
L->H Data Out (Q)
L->H Data Out (Q)
L->H Three-State
L->H Three-State
L->H Data In (D)
L->H Data In (D)
L->H Three-State
L->H Three-State
L->H
2t
2t
Max.
35
X
CYC
CYC
X
= Three-state when
Page 13 of 32
Three-State
Address
Fourth
A1: A0
DQ
11
00
01
10
Unit
-
mA
ns
ns
ns
ns
[+] Feedback