CY7C1354A-200BGC Cypress Semiconductor Corp, CY7C1354A-200BGC Datasheet - Page 7

• Manufacturer Part Number: CY7C1354A-200BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-200BGC

• Density: 9Mb
• Access Time (max): 3.2ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Supply Current: 560mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.47V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05161Rev. *E
Pin Descriptions—512K × 18
8, 9, 12, 13, 18,
58, 59, 62, 63,
68, 69, 72, 73,
14, 15, 16, 41,
26, 40, 55, 60,
19, 22, 23, 24
67, 71, 76, 90
54, 61, 70, 77
5, 10, 17, 21,
4, 11, 20, 27,
TQFP Pins
512K × 18
65, 66, 91
98,
88
89
92
97
86
85
31
64
74
38
39
43
42
7G, 6H, 7K, 6L,
1H, 2K, 1L, 2M,
3D, 5D, 3E, 5E,
5H, 3K, 5K, 3L,
1J, 7J, 1M, 7M,
(b) 1D, 2E, 2G,
3F, 5F, 5G, 3H,
1A, 7A, 1F, 7F,
(a) 6D, 7E, 6F,
4C, 2J, 4J, 6J,
3M, 5M, 3N,
PBGA Pins
5N, 3P, 5P
512K × 18
6N, 7P
1N, 2P
4R, 5R
1U, 7U
4E, 6B
4H
4K
2B
4B
3R
2U
3U
4U
5U
4F
7T
Name
WEN
MOD
V
TMS
TDO
CLK
ADV
DQa
DQb
TCK
CE
CE
V
V
Pin
CE,
/LD
TDI
OE
ZZ
CCQ
E
CC
SS
3
2
(continued)
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronou
I/O Supply
Ground
Output
Output
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input/
Static
Type
Input
Input
s
Read Write: WEN signal is a synchronous input that identifies whether
the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the current
cycle takes place two clock cycles later.
Clock: This is the clock input to CY7C1356A. Except for OE, ZZ, and
MODE, all timing references for the device are made with respect to the
rising edge of CLK.
Synchronous Active LOW Chip Enable: CE and CE
CE
sampled LOW, along with ADV/LD LOW at the rising edge of clock,
initiates a deselect cycle. The data bus will be High-Z two clock cycles
after chip deselect is initiated.
Synchronous Active HIGH Chip Enable: CE
to enable the chip. CE
CE and CE
Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and write cycles. In normal operation,
OE can be tied LOW.
Advance/Load: ADV/LD is a synchronous input that is used to load the
internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN are
ignored when ADV/LD is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
Sleep Enable: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has to be
either LOW or NC.
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins.
IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or be
connected to V
IEEE 1149.1 Test Inputs: LVTTL-level output. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect).
Power Supply: +3.3V –5% and +5%.
Ground: GND.
Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V
–0.125V and +0.4V for 2.5V I/O.
2
to enable the CY7C1356A. CE or CE
3
.
CC
.
2
has inverted polarity but otherwise is identical to
Pin Description
3
sampled HIGH or CE
2
is used with CE and CE
CY7C1354A
CY7C1356A
3
are used with
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