CY7C1354A-200BGC Cypress Semiconductor Corp, CY7C1354A-200BGC Datasheet - Page 20

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CY7C1354A-200BGC

Manufacturer Part Number
CY7C1354A-200BGC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1354A-200BGC

Density
9Mb
Access Time (max)
3.2ns
Operating Supply Voltage (typ)
3.3V
Package Type
BGA
Operating Temp Range
0C to 70C
Supply Current
560mA
Operating Supply Voltage (min)
3.14V
Operating Supply Voltage (max)
3.47V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
119
Word Size
36b
Lead Free Status / Rohs Status
Not Compliant
Document #: 38-05161Rev. *E
Switching Waveforms
Read Timing
Notes:
41. Q(A
42. CE
43. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
44. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN signal
45. BWc and BWd apply to 256K × 36 device only.
BWa#, BWb#
data in the burst sequence of the base address A
of the MODE input.
to the CE signal. For example, when CE is LOW on this waveform, CE
when new address and control are loaded into the SRAM.
BWa, BWb,
BWc, BWd
ADDRESS
3
ADV/LD#
1
timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE
) represents the first output from the external address A
ADV/LD
CKE#
R/W#
WEN
CEN
CLK
OE#
CE#
CE
OE
DQ
[41, 42, 43, 44, 45]
A
1
t
t
t
t
t
S
S
S
S
S
t
KQLZ
Pipeline Read
A
2
t
t
t
t
t
H
H
H
H
H
Pipeline Read
2
Q(A
, etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state
1
)
t
KQ
1
. Q(A
t
KC
Q(A
t
2
KL
) represents the first output from the external address A
2
)
2
is HIGH.
t
KQX
Q(A
2
+1)
t
KH
BURST PIPELINE READ
(CKE# HIGH , eliminates
current L-H clock edge)
3
Q(A
is LOW. CE
2
+2)
2
timing transitions are identical but inverted
2
; Q(A
Q(A
2
+1) represents the next output
(Burst Wraps around
2
+3)
to initial state)
CY7C1354A
CY7C1356A
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Q(A
2
)
t
KQHZ

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