CY7C1347F-166AC Cypress Semiconductor Corp, CY7C1347F-166AC Datasheet - Page 11

• Manufacturer Part Number: CY7C1347F-166AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347F-166AC

• Density: 4.5Mb
• Access Time (max): 3.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 17b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 240mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05213 Rev. *D
Switching Waveforms
Read Cycle Timing
Notes:
17. On this diagram when CE is LOW, CE
18. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW
Data Out (Q)
GW, BWE,
ADDRESS
BW
ADSP
ADSC
ADV
[A:D]
CLK
OE
CE
t
ADS
[17]
t AS
t CES
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
1
t CO
is LOW, CE
t ADS
A2
Q(A1)
t ADH
t OEHZ
2
is HIGH and CE
t ADVS
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
3
t DOH
is LOW. When CE is HIGH,CE
t CO
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
[A:D]
Q(A2 + 2)
LOW.
BURST READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
Q(A2 + 1)
3
CY7C1347F
is HIGH.
t CHZ
Deselect
cycle
Page 11 of 19
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