CY7C1347F-166AC Cypress Semiconductor Corp, CY7C1347F-166AC Datasheet
CY7C1347F-166AC
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CY7C1347F-166AC Summary of contents
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... The CY7C1347F is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347F I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... DDQ V SSQ BYTE SSQ V DDQ DQP D Document #: 38-05213 Rev. *D -250 -225 -200 2.6 2.6 2.8 325 290 265 100-Pin TQFP CY7C1347F CY7C1347F -166 -133 Unit 3.5 4.0 ns 240 225 DQP DDQ 76 V SSQ BYTE SSQ 70 V DDQ DDQ V 60 SSQ 59 DQ ...
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... Document #: 38-05213 Rev. *D 119-Ball BGA ADSP ADSC DQP ADV CLK BWE DQP MODE 165-Ball fBGA BWE CLK CY7C1347F DDQ DQP DDQ DDQ DDQ DQP DDQ ADSC ADV NC OE ADSP DQP SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP SS DDQ Page [+] Feedback ...
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... Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and DDQ should remain static during device operation. Mode Pin has an internal pull-up. No Connects. CY7C1347F , CE , and ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data 1 to the DQs and DQPs inputs. Doing so will three-state the ...
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... and BWE = WRITE = H when all Byte write enable signals CY7C1347F Second Third Fourth Address Address Address A A [1:0] [1:0] [1: Min. Max. Unit CYC 2t ns CYC 2t ns CYC CLK L-H three-state L-H three-state L-H three-state L-H three-state L-H three-state three-state L L-H three-state ...
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... Write All Bytes Notes: 7. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05213 Rev ADSP ADSC ADV WRITE [ BWE valid. Appropriate write will be done based on which byte write is active. [A:D] CY7C1347F DQ OE CLK L L Page [+] Feedback ...
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... MHz , Device Deselected, All speeds DD ≤ 0. > V – 0.3V DDQ /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < V and CY7C1347F DDQ 3.3V −5%/+10% 2.5V − Min. Max. Unit 3.135 3.6 V 2.375 ...
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... R = 317Ω 3.3V V DDQ OUTPUT GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ OUTPUT GND =1538Ω INCLUDING JIG AND SCOPE (b) TQFP Test Conditions Package 41.83 9.99 CY7C1347F Min. Max. Unit 105 mA 100 BGA fBGA Package Package Unit ...
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... V and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V on all data sheets. DDQ CY7C1347F -166 -133 Min. Max. Min. Max. Unit ...
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... OEV OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH, LOW. [A:D] CY7C1347F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...
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... CEH CE ADV Data In (D) High-Z t OEHZ t CLZ Data Out (Q) Q(A1) Q(A2) High-Z Back-to-Back READs Document #: 38-05213 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1347F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... The data bus (Q)remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20 HIGH Document #: 38-05213 Rev WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1347F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...
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... Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05213 Rev ZZREC t RZZI DESELECT or READ Only High-Z DON’T CARE CY7C1347F Page [+] Feedback ...
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... CY7C1347F-250AC CY7C1347F-250BGC 225 CY7C1347F-225AC CY7C1347F-225BGC 200 CY7C1347F-200AC CY7C1347F-200BGC CY7C1347F-200BZC CY7C1347F-200AI CY7C1347F-200BGI 166 CY7C1347F-166AC CY7C1347F-166BGC CY7C1347F-166BZC CY7C1347F-166AI CY7C1347F-166BGI 133 CY7C1347F-133AC CY7C1347F-133BGC CY7C1347F-133BZC CY7C1347F-133AI CY7C1347F-133BGI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05213 Rev. *D ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05213 Rev. *D CY7C1347F 51-85050-*A Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 38-05213 Rev. *D 119-Lead PBGA ( 2.4 mm) BG119 CY7C1347F 51-85115-*B Page [+] Feedback ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA ( 1.20 mm) BB165C 0.15(4X) CY7C1347F PIN 1 CORNER BOTTOM VIEW Ø0. Ø0. Ø0.45±0.05(165X ...
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... Document History Page Document Title: CY7C1347F 4-Mbit (128K x 36) Pipelined Sync SRAM Document Number: 38-05213 Orig. of REV. ECN NO. Issue Date Change ** 119829 12/16/02 *A 123117 01/18/03 *B 127632 06/13/03 *C 200660 See ECN *D 213342 See ECN Document #: 38-05213 Rev. *D Description of Change HGK New Data Sheet ...