CY7C1312AV18-133BZC Cypress Semiconductor Corp, CY7C1312AV18-133BZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1312AV18-133BZC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1312AV18-133BZC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Document #: 38-05497 Rev. *A
Pin Definitions
Q
RPS
C
C
K
K
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
V
V
V
SS
SS
SS/
[x:0]
Pin Name
/72M
/144M
288M
(continued)
Synchronous
Synchronous
Input-Clock
Input-Clock
Input-Clock
Input-Clock
Echo Clock
Echo Clock
Outputs-
Output
Input-
Input
Input
Input
Input
Input
Input
Input
Input
N/A
N/A
N/A
I/O
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q
CY7C1310AV18 − Q
CY7C1312AV18 − Q
CY7C1314AV18 − Q
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q
are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ,CQ and Q
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
be connected directly to GND or left unconnected.
DLL Turn Off – Active LOW. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. More details on this operation can be found in the application note,
“DLL Operation in the QDR-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Address expansion for 36M. This is not connected to the die and so can be tied to any
voltage level.
Address expansion for 72M. This is not connected to the die and so can be tied to any
voltage level.
Address expansion for 72M. This must be tied LOW on the 18M devices.
Address expansion for 144M. This must be tied LOW on the 18M devices.
Address expansion for 288M. This must be tied LOW on the 18M devices.
[x:0]
are automatically tri-stated.
PRELIMINARY
[7:0]
[17:0]
[35:0]
DD
, which enables the minimum impedance mode. This pin cannot
Pin Description
[x:0]
[x:0]
[x:0]
when in single clock mode. All accesses
output impedance are set to 0.2 x RQ,
when in single clock mode.
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
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