CY7C1018CV33-15VC Cypress Semiconductor Corp, CY7C1018CV33-15VC Datasheet - Page 3

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CY7C1018CV33-15VC

Manufacturer Part Number
CY7C1018CV33-15VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1018CV33-15VC

Lead Free Status / Rohs Status
Not Compliant
Document #: 38-05131 Rev. *C
AC Test Loads and Waveforms
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes:
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of any of these
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
5.
6.
7.
8.
9.
Parameter
[9]
[9]
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thèvenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
t
At any given temperature and voltage condition, t
This parameter is guaranteed by design and is not tested.
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
8-ns devices:
HZOE
GND
3.0V
, t
Rise Time: 1 V/ns
HZCE
OUTPUT
[10, 11]
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address
Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
WE LOW to High-Z
HZWE
are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
Description
10%
90%
Z = 50
ALL INPUT PULSES
[8]
[7, 8]
[8]
[7, 8]
[7, 8]
Over the Operating Range
(a)
(c)
1.5V
50
[5]
HZCE
is less than t
7C1018CV33-8
Min.
Fall Time: 1 V/ns
8
3
0
3
0
8
7
7
0
0
6
5
0
3
90%
30 pF*
10%
LZCE
Max.
[6]
, t
8
8
5
4
4
8
4
HZOE
is less than t
7C1018CV33-10 7C1018CV33-12 7C1018CV33-15
Min.
10
10
3
3
0
8
7
5
3
0
8
0
0
0
10-, 12-, 15-ns devices:
LZOE
High-Z characteristics:
OUTPUT
OUTPUT
, and t
Max.
HZWE
10
10
10
5
5
5
5
3.3V
3.3V
HZWE
and t
is less than t
SD
Min.
30 pF
12
12
.
5 pF
3
0
3
0
9
9
0
0
8
6
0
3
(d)
(b)
LZWE
Max.
R 317
R 317
12
12
12
6
6
6
6
for any given device.
CY7C1018CV33
351
351
Min.
R2
15
15
10
10
10
R2
3
0
3
0
0
0
8
0
3
Max.
Page 3 of 7
15
15
15
7
7
7
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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