CY7C1018CV33-15VC Cypress Semiconductor Corp, CY7C1018CV33-15VC Datasheet

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CY7C1018CV33-15VC

Manufacturer Part Number
CY7C1018CV33-15VC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1018CV33-15VC

Lead Free Status / Rohs Status
Not Compliant
Cypress Semiconductor Corporation
Document #: 38-05131 Rev. *C
Features
Functional Description
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Selection Guide
Note:
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
1.
• Pin- and function-compatible with CY7C1018BV33
• High speed
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 300-mil-wide 32-pin SOJ
Logic Block Diagram
WE
CE
OE
— t
For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
A
A
A
A
A
A
A
A
A
AA
0
1
2
3
4
5
6
7
8
= 8, 10, 12, 15 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
[1]
7C1018CV33-8
POWER
DOWN
95
8
5
3901 North First Street
7C1018CV33-10
10
90
5
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
0
San Jose
through I/O
7C1018CV33-12
128K x 8 Static RAM
12
85
I/O
I/O
V
V
I/O
I/O
WE
5
CE
CC
A
A
A
A
A
A
A
A
SS
7
0
1
2
0
1
2
3
4
5
6
3
7
Pin Configurations
) is then written into the location
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CA 95134
Top View
0
SOJ
Revised September 13, 2002
0
through I/O
through A
7C1018CV33-15
CY7C1018CV33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
15
80
5
16
7
A
A
A
A
OE
I/O
I/O
V
V
I/O
I/O
A
A
A
A
A
) are placed in a
).
SS
CC
16
15
14
13
12
11
10
9
8
408-943-2600
7
6
5
4
Unit
mA
mA
ns

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CY7C1018CV33-15VC Summary of contents

Page 1

... I/O pins. The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1018CV33 is available in a standard 300-mil-wide SOJ. I/O 0 I/O 1 ...

Page 2

... V < MAX Max > V – 0.3V > V – 0.3V < 0.3V Test Conditions T = 25° MHz 3.3V CC CY7C1018CV33 [2] ................................ –0. Ambient Temperature 0°C to +70°C 7C1018CV33 7C1018CV33 7C1018CV33 -10 -12 -15 Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.0 V 2 0.3 + 0.3 – ...

Page 3

... Document #: 38-05131 Rev. *C [5] 10-, 12-, 15-ns devices pF* 1.5V (a) High-Z characteristics: 90% 10% Fall Time: 1 V/ns (c) [6] 7C1018CV33-8 7C1018CV33-10 7C1018CV33-12 7C1018CV33-15 Min. Max. Min less than less than t HZCE LZCE HZOE LZOE CY7C1018CV33 R 317 3.3V OUTPUT 351 (b) R 317 3.3V OUTPUT 351 (d) Max. Min. Max. Min ...

Page 4

... Data I/O is high impedance 16 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05131 Rev OHA ACE t DOE t LZOE 50 SCE PWE DATA VALID . IL CY7C1018CV33 DATA VALID t HZOE t HZCE DATA VALID t PD 50% t SCE HIGH IMPEDANCE ICC ISB Page ...

Page 5

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05131 Rev. *C [15, 16 SCE PWE t SD DATA [11, 16 SCE PWE t HZWE –I/O Mode 0 7 Power-down Power-down Read Write Selected, Outputs Disabled CY7C1018CV33 VALID DATA VALID t LZWE Power Standby (I SB Standby (I SB Active (I CC Active (I CC Active ( Page ...

Page 6

... CY7C1018CV33-10VC 12 CY7C1018CV33-12VC 15 CY7C1018CV33-15VC Package Diagram All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05131 Rev. *C © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 7

... Document History Page Document Title: CY7C1018CV33 128K x 8 Static RAM Document Number: 38-05131 Issue REV. ECN NO. Date ** 109426 12/14/01 *A 113432 04/10/02 *B 115046 05/30/02 *C 116476 09/16/02 Document #: 38-05131 Rev. *C Orig. of Change HGK New Data Sheet NSL AC Test Loads split based on speed HGK ...

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