CY62157CV30LL-70BAI Cypress Semiconductor Corp, CY62157CV30LL-70BAI Datasheet - Page 6

• Manufacturer Part Number: CY62157CV30LL-70BAI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62157CV30LL-70BAI

• Density: 8Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 19b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 12mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.3V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05014 Rev. *E
Switching Characteristics
Switching Waveforms
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
Notes:
10. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
11. At any given temperature and voltage condition, t
12. t
13. When both byte enables are toggled together this value is 10 ns.
14. The internal Write time of the memory is defined by the overlap of WE, CE
15. Device is continuously selected. OE, CE
16. WE is HIGH for Read cycle.
Read Cycle No. 1 (Address Transition Controlled)
DATA OUT
ADDRESS
specified I
any given device.
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
HZOE
[11]
Parameter
, t
HZCE
OL
[14]
/I
, t
OH
HZBE
and 30-pF load capacitance.
, and t
PREVIOUS DATA VALID
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE
CE
CE
CE
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z
BHE/BLE HIGH to High-Z
Write Cycle Time
CE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE/BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
transitions are measured when the outputs enter a high-impedance state.
1
1
1
1
1
1
LOW and CE
LOW and CE
HIGH or CE
LOW and CE
HIGH or CE
LOW and CE
Over the Operating Range
1
= V
IL
Description
, BHE and/or BLE = V
t
OHA
HZCE
2
2
2
2
2
2
LOW to High-Z
LOW to Power-down
[11]
HIGH to Data Valid
[11, 12]
HIGH to Low-Z
HIGH to Power-up
HIGH to Write End
[11, 12]
[11]
is less than t
t
AA
[13]
[11, 12]
[15, 16]
LZCE
IL
, CE
[11, 12]
, t
[11]
[10]
1
HZBE
2
= V
= V
IL
t
is less than t
IH
RC
, BHE and/or BLE = V
.
Min.
55
10
10
55
45
45
45
50
25
CC(typ.)
5
0
5
0
0
0
5
55 ns
LZBE
/2, input pulse levels of 0 to V
, t
HZOE
Max.
55
55
25
20
20
55
55
20
20
IL
, CE
is less than t
2
= V
CY62157CV25/30/33
IH
. All signals must be ACTIVE to initiate a
DATA VALID
Min.
LZOE
70
70
10
10
60
60
50
60
30
5
0
5
0
0
0
5
, and t
70 ns
CC(typ.)
HZWE
, and output loading of the
Max.
70
70
35
25
25
70
70
25
25
is less than t
Page 6 of 12
LZWE
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
for
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