CY62148DV30LL-70SXI Cypress Semiconductor Corp, CY62148DV30LL-70SXI Datasheet - Page 5

• Manufacturer Part Number: CY62148DV30LL-70SXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62148DV30LL-70SXI

• Density: 4Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 19b
• Package Type: SOIC
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Compliant

Document #: 38-05341 Rev. *D
Switching Characteristics
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Notes:
10. Test Conditions for all parameters other than three-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
11. At any given temperature and voltage condition, t
12. t
13. The internal write time of the memory is defined by the overlap of WE, CE = V
14. Device is continuously selected. OE, CE = V
15. WE is HIGH for read cycle.
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
DATA OUT
input pulse levels of 0 to V
terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
ADDRESS
HZOE
Parameter
, t
HZCE
[13]
, and t
HZWE
transitions are measured when the output enter a high impedance state.
CC(typ)
PREVIOUS DATA VALID
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-up
CE HIGH to Power-up
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
, and output loading of the specified I
(Over the Operating Range)
IL
Description
.
HZCE
t
OHA
[11]
[11]
[11, 12]
[11, 12]
[11]
[11,12]
is less than t
t
AA
[14, 15]
LZCE
OL
/I
, t
OH
HZOE
[10]
as shown in the
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
is less than t
t
RC
Min
55
10
10
55
40
40
40
25
10
5
0
0
0
0
55 ns
LZOE
“AC Test Loads and Waveforms” on page
, and t
Max
55
55
25
20
20
55
20
HZWE
is less than t
DATA VALID
Min
70
10
10
70
45
45
45
30
10
5
0
0
0
0
LZWE
70 ns
for any given device.
CY62148DV30
4.
Max
70
70
35
25
25
70
25
Page 5 of 10
CC(typ)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/2,