CY62147VLL-70ZI Cypress Semiconductor Corp, CY62147VLL-70ZI Datasheet - Page 4

• Manufacturer Part Number: CY62147VLL-70ZI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62147VLL-70ZI

• Density: 4Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 15mA
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05050 Rev. *A
Data Retention Waveform
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
11. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
5.
6.
7.
8.
9.
Full Device AC operation requires linear V
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
specified I
At any given temperature and voltage condition, t
If both byte enables are toggled together this value is 10ns
t
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
HZOE
[8]
V
, t
CE
CC
Parameter
HZCE
OL
[10, 11]
, and t
/I
OH
and 30 pF load capacitance.
HZWE
are specified with C
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
WE HIGH to Low-Z
Over the Operating Range[
CC
L
ramp from V
= 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
V
CC(min.)
t
CDR
HZCE
is less than t
DR
[7, 9]
[7]
Description
[9]
[7, 9]
[7, 9]
[7]
to V
CC(min.)
LZCE
DATA RETENTION MODE
, t
> 10 s or stable at V
6]
HZOE
is less than t
V
DR
> 1.0 V
HZWE
LZOE
CC(min.)
and t
, and t
SD
>10 s.
HZWE
.
Min.
70
10
10
70
60
60
40
60
30
10
5
0
5
0
0
0
is less than t
V
70 ns
CC(min.)
CY62147V MoBL
CC(typ.)
t
R
LZWE
Max.
, and output loading of the
70
70
25
20
20
70
70
20
25
for any given device.
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
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