IMIZ9974CA Cypress Semiconductor Corp, IMIZ9974CA Datasheet - Page 3

• Manufacturer Part Number: IMIZ9974CA
• Manufacturer: Cypress Semiconductor Corp

Specifications of IMIZ9974CA

• Number Of Outputs: 15
• Operating Supply Voltage (max): 3.47V
• Operating Temp Range: -40C to 85C
• Propagation Delay Time: 0.1ns
• Operating Supply Voltage (min): 3.14V
• Mounting: Surface Mount
• Pin Count: 52
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07090 Rev. *C
Pin Description
2
3
7, 5, 4
6
8
9,10
14,20
16,18,21,23,
25
29
31
32,34,36,48,
40
44,46,48,50
52
11,27,42
12
15
13
17,22,26
19,24
28
30
33,37,41
Note:
1.
A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins,
their high-frequency filtering characteristic will be cancelled by the lead inductances of the traces.
Pin
MR#
OE
fsel(a,b, c)
PLL_EN
TCLK_sel
TCLK(0:1)
fselFB(0:1)
Qa(0:4)
QFB
FB_In
Qb(0:4)
Qc(0:3)
VCO_Sel
n/c
VDDI
VSSI
VDDA
VDDa
VSSa
VDDFB
VSSFB
VDDb
Name
[1]
VDDa
VDDFB O
VDDb
VDDc
PWR
I
I
I
I
I
I
I
O
I
O
O
I
-
P
P
P
P
P
P
P
P
I/O
Master Reset pin. Active LOW. It has a 250-K internal pull-up. When forced
LOW, all outputs are three-stated (high impedance) and internal dividers are
reset.
Output Enable pin. Active LOW. It has a 250-K internal pull-up. When forced
LOW, Qa(0:4), Qb(0:4), and Qc(0:3) outputs are stopped in a LOW state. QFB
is not affected by this control signal.
Input select pins for setting the output dividers of Qa(0:4), Qb(0:4), and Qc(0:3)
respectively. Each pin has an internal 250-K pull-down. See Table 2 for output
divide ratios.
Input pin for bypassing the PLL. It has an internal 250-K pull-up. When forced
LOW, the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL
and drives the dividers, typically for device testing.
Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel
= 0, TCLK0 is selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a
250-k internal pull-down.
Input pins for applying a reference clock to the PLL. The active input is
selected by TCLK_sel, pin# 8. TCLK0 has a 250-K internal pull-down. TCLK1
has a 250-K internal pull-up.
Input select pins for setting the Feedback divide ratio at QFB output,
pin #29. See Table 1. Each of these pins has a 250-K internal pull-down.
High-drive, low-voltage CMOS, output clock buffers, Bank Qa. Their divide
ratio is programmed by fsela, pin #7.
Low-voltage CMOS output feedback clock to the internal PLL. The divide
ratio for this output is set by fselFB(0:1). A delay capacitor or trace may be applied
to this pin in order to control the Input Reference/Output Banks phase relation-
ship.
Feedback input pin. Typically connects to the QFB output for accessing the
feedback to the PLL. It has a 250-k
High-drive, low-voltage CMOS, output clock buffers, Bank Qb. Their divide
ratio is programmed by fselb, pin #4.
High-drive, low-voltage CMOS, output clock buffers, Bank Qc. Their divide
ratio is programmed by fselc, pin #5.
Input select pin for setting the divider of the VCO output. It has a 250-k
internal pull-down. If VCO_sel = 0, then the PLL VCO output is divided by 2. If
VCO_sel = 1, then the PLL VCO output is divided by 4. See Table 1 and Table 2.
These pins are not connected internally. They may be attached to a ground
plane.
Power for input logic circuitry.
Ground for input logic circuitry.
Power and Ground supply pins for internal analog circuitry.
3.3V supply for Qa(0:4) output bank, and fselFB1 input.
Common ground for Qa(0:4) output bank, and fselFB1 input.
Power supply pin for QFB output and FB_In input pins and digital circuitry.
Ground supply pin for QFB output and FB_In input pins and digital circuitry.
3.3V supply for Qb(0:4) output bank.
Description
internal pull-up.
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