CY7B994V-2AI Cypress Semiconductor Corp, CY7B994V-2AI Datasheet - Page 4

• Manufacturer Part Number: CY7B994V-2AI
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay PLL Clock Bufferr

Specifications of CY7B994V-2AI

• Number Of Elements: 1
• Supply Current: 250mA
• Pll Input Freq (min): 24MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 24 to 200MHz
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07127 Rev. *F
Pin Definitions
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+,
generated to control the frequency of the voltage-controlled
oscillator (VCO). These two blocks, along with the VCO, form
a PLL that tracks the incoming REF signal.
The CY7B993V/994V have a flexible REF and FB input
scheme. These inputs allow the use of either differential
LVPECL or single-ended LVTTL inputs. To configure as
single-ended LVTTL inputs, the complementary pin must be
left open (internally pulled to 1.5V). The other input pin can
then be used as an LVTTL input. The REF inputs are also
tolerant to hot insertion.
FBKA–, FBKB+, or FBKB–). Correction information is then
FBDS[0:1]
FBDIS
[1:4]F[0:1]
[1:4]DS[0:1]
DIS[1:4]
INV3
LOCK
OUTPUT_MODE Input
QFA[0:1]
[1:4]Q[A:B][0:1]
VCCN
VCCQ
GND
Pin Name
Input
Input
Input
Input
Input
Input
Output LVTTL
Output LVTTL
Output LVTTL
(continued)
I/O
Pin Type
3-level
Input
LVTTL
3-level
Input
3-level
Input
LVTTL
3-level
Input
3-Level
Input
PWR
PWR
PWR
[1]
Feedback Divider Function Select: These inputs determine the function of the QFA0
and QFA1 outputs (see Table 4).
Feedback Disable: This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]
is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Table 5). This input has an
internal pull-down.
Output Phase Function Select: Each pair controls the phase function of the respective
bank of outputs (see Table 3).
Output Divider Function Select: Each pair controls the divider function of the respective
bank of outputs (see Table 4).
Output Disable: Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see Table 5).
These inputs each have an internal pull-down.
Invert Mode: This input only affects Bank 3. When this input is LOW, each matched output
pair will become complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is
HIGH, all four outputs in the same bank will be inverted. When this input is MID all four
outputs will be non inverting.
PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
Output Mode: This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs will disable to high-impedance (HI-Z). When this input is LOW,
the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter
factory test mode.
Clock Feedback Output: This pair of clock outputs is intended to be connected to the
FB input. These outputs have numerous divide options and three choices of phase adjust-
ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.
Clock Output: These outputs provide numerous divide and phase select functions deter-
mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.
Output Buffer Power: Power supply for each output pair.
Internal Power: Power supply for the internal circuitry.
Device Ground.
The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency,
the PLL is optimized to ensure that the clock output period will
not be less than the calculated system budget (t
(nominal reference clock period) – t
t
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter
block. The FS control pin setting determines the nominal
operational frequency range of the divide by one output (f
of the device. f
There are two versions: a low-speed device (CY7B993V)
where f
high-speed device (CY7B994V) that ranges from 24 MHz to
200 MHz. The FS setting for each device is shown in Table 1.
The f
the CY7B994V, the upper f
200 MHz.
PDEV
NOM
(max. period deviation)) while reacquiring the lock.
NOM
Pin Description
frequency is seen on “divide-by-one” outputs. For
ranges from 12 MHz to 100 MHz, and a
NOM
is directly related to the VCO frequency.
NOM
range extends from 96 MHz to
CCJ
RoboClock
(cycle-to-cycle jitter) –
CY7B993V
CY7B994V
Page 4 of 15
MIN
= t
NOM

REF
)
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