CY7B9945V-2AI Cypress Semiconductor Corp, CY7B9945V-2AI Datasheet - Page 4

• Manufacturer Part Number: CY7B9945V-2AI
• Manufacturer: Cypress Semiconductor Corp
• Type: PLL Clock Bufferr

Specifications of CY7B9945V-2AI

• Number Of Elements: 1
• Supply Current: 250mA
• Pll Input Freq (min): 24MHz
• Pll Input Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TQFP
• Output Frequency Range: 24 to 200MHz
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Industrial
• Pin Count: 52
• Lead Free Status / Rohs Status: Not Compliant

Table 4. Output Divider Select
Output Disable Description
The output of each output bank can be independently put into a
HOLD OFF or high impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks are enabled. When DIS[1:2] is HIGH, the
Document Number: 38-07336 Rev. *G
and FBDS1
(N/A)
(N/A)
(N/A)
1F[3:2]
(N/A)
(N/A)
(N/A)
1F[1:0]
MM
LM
LH
ML
MH
HL
HM
LL
HH
[1:2]DS1
HIGH
HIGH
HIGH
MID
MID
MID
Control Signal
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
2F[1:0]
MM
HL
LL
LM
HM
LH
HH
[1:2]DS0
FBDS0
HIGH
HIGH
LOW
LOW
MID
MID
and
REFInput
FBInput
+1t
+2t
+3t
+6t
+7t
+8t
–2t
+4t
–8t
–7t
–6t
–4t
–3t
–1t
0t
Bank1
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
/ 10
/ 12
/ 4
/ 5
/ 6
/ 8
Output Divider Function
Bank2
/ 10
/ 12
/ 4
/ 5
/ 6
/ 8
Feedback
PRELIMINARY
/ 10
/ 12
/ 4
/ 5
/ 6
/ 8
Figure 2
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0t
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole t
example, if the output used for feedback is programmed to shift
–4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8t
outputs for that bank are disabled to a high impedance (HI-Z) or
HOLD OFF state.
The HOLD OFF state is a power saving feature. An output bank
is disabled to the HOLD OFF state in a maximum of six output
clock cycles from the time the disable input is HIGH. When
disabled to the HOLD OFF state, outputs are driven to a logic
LOW state on their falling edges. This makes certain that the
output clocks are stopped without a glitch. When a bank of
shows the timing relationship of programmable skew
U
with respect to REF.
Table 5
U
defines the disabled outputs functions.
matrix shifts with respect to REF. For
[3]
RoboClock
CY7B9945V
U
skew. The PLL
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