CY7B9945V-2AI Cypress Semiconductor Corp, CY7B9945V-2AI Datasheet

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CY7B9945V-2AI

Manufacturer Part Number
CY7B9945V-2AI
Description
Manufacturer
Cypress Semiconductor Corp
Type
PLL Clock Bufferr
Datasheet

Specifications of CY7B9945V-2AI

Number Of Elements
1
Supply Current
250mA
Pll Input Freq (min)
24MHz
Pll Input Freq (max)
200MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TQFP
Output Frequency Range
24 to 200MHz
Operating Supply Voltage (min)
2.97V
Operating Supply Voltage (max)
3.63V
Operating Temperature Classification
Industrial
Pin Count
52
Lead Free Status / Rohs Status
Not Compliant
Features
Cypress Semiconductor Corporation
Document Number: 38-07336 Rev. *G
Logic Block Diagram
500 ps max Total Timing Budget (TTB™) window
24 MHz –200 MHz input and Output Operation
Low Output-output skew <200 ps
10 + 1 LVTTL Outputs driving 50Ω terminated lines
Dedicated feedback output
Phase adjustments in 625ps/1300 ps steps up to +10.4 ns
3.3V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable
Reference Inputs
Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
Individual Output Bank Disable
Output High Impedance Option for Testing Purposes
Integrated Phase Locked Loop (PLL) with Lock Indicator
Low Cycle-cycle jitter (<100 ps peak-peak)
3.3V Operation
Industrial Temperature Range: –40°C to +85°C
52-pin 1.4 mm TQFP package
R E F S E L
M O D E
R E F A +
R E F A -
R E F B +
R E F B -
F B K
F S
3
PRELIMINARY
F B D S 0
F B D S 1
High Speed Multi-phase PLL Clock Buffer
198 Champion Court
F B F 0
1 D S 0
1 D S 1
2 D S 0
2 D S 1
1 F 0
1 F 1
1 F 2
1 F 3
2 F 0
2 F 1
P L L
3
3
3
3
3
3
3
3
3
3
3
3
3
D iv id e
P h a s e
S e le c t
D iv id e
P h a s e
S e le c t
D iv id e
P h a s e
S e le c t
a n d
a n d
a n d
Functional Description
The CY7B9945V high speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window speci-
fying all occurrences of output clocks. This includes the input
reference clock across variations in output frequency, supply
voltage, operating temperature, input edge rate, and process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in 625
ps–1300 ps increments up to ±10.4 ns. The dedicated feedback
output enables divide-by functionality from 1 to 12 and limited
phase adjustments. However, if needed, any one of the ten
outputs can be connected to the feedback input as well as driving
other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
D IS 1
D IS 2
San Jose
L O C K
1 Q 0
1 Q 1
1 Q 2
Q F
1 Q 3
2 Q 0
2 Q 1
2 Q 2
2 Q 3
2 Q 4
2 Q 5
,
CA 95134-1709
Revised September 10, 2009
RoboClock
CY7B9945V
408-943-2600
®
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CY7B9945V-2AI Summary of contents

Page 1

... PRELIMINARY High Speed Multi-phase PLL Clock Buffer Functional Description The CY7B9945V high speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer and communication systems ...

Page 2

... FBDS[0:1] and FBF0, respectively. See Table 3 and Table 4. LVTTL PLL Lock Indicator. When HIGH, this output indicates that the internal PLL is locked to the reference signal. When LOW, it indicates that the PLL is attempting to acquire lock RoboClock CY7B9945V 39 REFA- 38 REFSEL 37 REFB- 36 REFB+ 35 1F2 ...

Page 3

... The PLL adjusts the phase and the frequency of its output signal to minimize the delay between the reference (REFA/B+, REFA/B-) and the feedback (FB) input signals. The CY7B9945V has a flexible REF input scheme. These inputs enable the use of either differential LVPECL or single ended LVTTL inputs. To configure as single ended LVTTL inputs, leave the complementary pin open (internally pulled to 1 ...

Page 4

... HIGH. When disabled to the HOLD OFF state, outputs are driven to a logic LOW state on their falling edges. This makes certain that the output clocks are stopped without a glitch. When a bank of RoboClock CY7B9945V skew. The PLL U matrix shifts with respect to REF. For U ...

Page 5

... MODE LOW MID ENABLED HI the V and Phase Generator. f NOM CO when the output connected undivided. NOM ® RoboClock CY7B9945V DIS[1:2] 1Q[0:3], 2Q[0:5] HIGH HOLD-OFF X FACTORY TEST always appears on an output when the output NOM ). Internal termination resistors hold the CC time before LOCK ...

Page 6

... MHz is 6. Figure 3. Typical Safe Operating Zone Typical Safe Operating Zone (25-pF Load, 0-m/s air flow) 100 Safe Operating Zone Number of Outputs at 185 MHz ® RoboClock CY7B9945V Page [+] Feedback ...

Page 7

... IN –400 400 1.0 GND 0.8 [ Max, f – CC MAX V = Max – CC LOAD pF 50Ω /2, LOAD CC f MAX ® RoboClock CY7B9945V V CC ° ° 3.3V ±10 +70 C ° ° 3.3V ±10% – +85 C Max Unit – V – V 0.5 V 0.5 V μA 100 V + 0.3 ...

Page 8

... MHz 3. Description [12, 13] [12, 13] and SKEW0 [14, 15] [16] [5] [5] [11] [19] [19] [20] [12, 21] [21, 22] RoboClock CY7B9945V Min Max Unit – CY7B9945V-2 CY7B9945V-5 Unit Min Max Min Max 24 200 24 200 MHz 24 200 24 200 MHz – 200 – 200 ps – 250 – 250 ps – 250 – ...

Page 9

... LVTTL AC Test Load 2.0V 2.0V 0.8V < (b) TTL Input Test Waveform Figure 5. AC Timing Diagram t SKEWPR t PWL 0.8V t CCJ1-3,4-12 [1:2]Q[0:3] t SKEWBNK [1:2]Q[0: SKEW0,1 Other 185 MHz 200 MHz L RoboClock CY7B9945V [22] 3. 0.8V < [1:2]Q[0,2] t SKEWPR [1:2]Q[1,3] t SKEWBNK t ODCV t ODCV t SKEW0,1 Page ® [+] Feedback ...

Page 10

... Ordering Information Propagation Max. Speed Ordering Code Delay (ps) (MHz) 250 200 CY7B9945V-2AC 500 200 CY7B9945V-5AC 250 200 CY7B9945V-2AI 200 CY7B9945V-2AIT 500 200 CY7B9945V-5AI Pb-free 250 200 CY7B9945V-2AXC 200 CY7B9945V-2AXCT 250 200 CY7B9945V-2AXI 200 CY7B9945V-2AXIT 500 200 CY7B9945V-5AXC 200 CY7B9945V-5AXCT Package Diagram Figure 6 ...

Page 11

... Document History Page Document Title: CY7B9945V RoboClock Document Number: 38-07336 Orig. of Submis- Revision ECN Change sion Date ** 111747 CTK 03/04/02 New Data Sheet *A 116572 HWT 09/05/02 Added TTB Features *B 119078 HWT 10/16/02 Corrected the following items in the Electrical Characteristics table: *C 124645 ...

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