CY62127DV30LL-55ZI Cypress Semiconductor Corp, CY62127DV30LL-55ZI Datasheet - Page 6

• Manufacturer Part Number: CY62127DV30LL-55ZI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY62127DV30LL-55ZI

• Density: 1Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 2.5/3.3V
• Address Bus: 16b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 10mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05229 Rev. *H
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1 (WE Controlled)
Notes:
16. Device is continuously selected. OE, CE = V
17. WE is HIGH for Read cycle.
18. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
19. Data I/O is high-impedance if OE = V
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
21. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
DATA OUT
ADDRESS
ADDRESS
DATA I/O
BHE/BLE
CE
WE
OE
DON'T CARE
PREVIOUS DATA VALID
IH
t
SA
.
t
HZOE
[16,17,18]
[14, 15, 19, 20, 21]
IL
, BHE, BLE = V
t
OHA
t
IL
AA
t
AW
.
[16,17]
t
SCE
t
WC
t
BW
t
RC
DATA
t
t
PWE
SD
IN
VALID
t
HA
DATA VALID
t
HD
CY62127DV30
Page 6 of 11
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