CY62127DV30LL-55ZI Cypress Semiconductor Corp, CY62127DV30LL-55ZI Datasheet - Page 5

CY62127DV30LL-55ZI

Manufacturer Part Number
CY62127DV30LL-55ZI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62127DV30LL-55ZI

Density
1Mb
Access Time (max)
55ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
16b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
10mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Word Size
16b
Number Of Words
64K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62127DV30LL-55ZI
Manufacturer:
CY
Quantity:
30 534
Document #: 38-05229 Rev. *H
Switching Characteristics
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes:
11. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
12. At any given temperature and voltage condition, t
13. If both byte enables are toggled together, this value is 10 ns.
14. t
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
specified I
given device.
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
HZOE
Parameter
[13]
, t
HZCE
OL
[15]
, t
.
HZBE
, and t
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-up
CE HIGH to Power-down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to High-Z
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
HZWE
transitions are measured when the outputs enter a high-impedance state.
Description
(Over the Operating Range)
[12]
[12]
[12,14]
[12,14]
[12]
[12,14]
HZCE
[12]
is less than t
[12,14]
CY62127DV30-45
LZCE
Min.
45
10
10
45
40
40
35
40
25
10
0
5
5
0
0
0
, t
HZBE
[11]
IL
is less than t
, BHE and/or BLE = V
Max.
45
45
25
15
20
45
45
15
15
CC(typ.)
[8]
LZBE
CY62127DV30-55
/2, input pulse levels of 0 to V
, t
Min.
HZOE
55
10
10
55
40
40
40
40
25
10
5
0
5
0
0
0
IL
. All signals must be ACTIVE to initiate a write and any
is less than t
Max.
55
55
25
20
20
55
55
20
20
LZOE
, and t
CY62127DV30-70
CC(typ.)
Min.
CY62127DV30
70
10
10
70
60
60
50
60
30
HZWE
5
0
5
0
0
0
5
, and output loading of the
is less than t
Max.
70
70
35
25
25
70
70
25
25
Page 5 of 11
LZWE
for any
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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