5962-9314401MZX Cypress Semiconductor Corp, 5962-9314401MZX Datasheet - Page 5

• Manufacturer Part Number: 5962-9314401MZX
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9314401MZX

• Memory Type: EPROM
• # Macrocells: 128
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Pin Count: 84
• Package Type: Windowed PGA
• Lead Free Status / Rohs Status: Not Compliant

I/O Block
Separate from the macrocell array is the I/O control block of
the LAB. Figure 6 shows the I/O block diagram. The
three-state buffer is controlled by a macrocell product term
and the drives the I/O pad. The input of this buffer comes
from a macrocell within the associated LAB. The feedback
path from the I/O pin may feed other blocks within the LAB, as
well as the PIA. By decoupling the I/O pins from the flip-flops,
all the registers in the LAB are “buried,” allowing the I/O pins
to be used as dedicated outputs, bidirectional outputs, or as
additional dedicated inputs. Therefore, applications requiring
many buried flip-flops, such as counters, shift registers, and
state machines, no longer consume both the macrocell regis-
ter and the associated I/O pin, as in earlier devices.
The Programmable Interconnect Array
PLD density and speed has traditionally been limited by signal
routing; i.e., getting signals from one macrocell to another. For
smaller devices, a single array is used and all signals are avail-
able to all macrocells. But as the devices increase in density,
the number of signals being routed becomes very large, in-
creasing the amount of silicon used for interconnections. Also,
because the signal must be global, the added loading on the
internal connection path reduces
the overall speed performance of the device. The MAX archi-
tecture solves these problems. It is based on the concept of
small, flexible logic array blocks that, in the larger devices, are
interconnected by a PIA.
The PIA solves interconnect limitations by routing only the sig-
nals needed by each LAB. The architecture is designed so that
every signal on the chip is within the PIA. The PIA is then
programmed to give each LAB access to the signals that it
requires. Consequently, each LAB receives only the signals
needed. This effectively solves any routing problems that may
arise in a design without degrading the performance of the
device. Unlike masked or programmable gate arrays, which
induce variable delays dependent on routing, the PIA has a
fixed delay from point to point. This eliminates undesired
skews among logic signals, which may cause glitches in inter-
nal or external logic.
Development Software Support
Warp
Warp is a state-of-the-art compiler and complete CPLD design
tool. For design entry, Warp provides an IEEE-STD-1076/1164
VHDL text editor, an IEEE-STD-1364 Verilog text editor and a
graphical finite state machine editor. It provides optimized syn-
thesis and fitting by replacing basic circuits with ones pre-op-
timized for the target device, by implementing logic in unused
memory and by perfect communication between fitting and
synthesis. Warp provides other tools such as graphical timing
simulation and analysis.
Warp Professional
Warp Professional contains several additional features. It pro-
vides an extra method of design entry with its graphical block
diagram editor. It allows up to 5 ms timing simulation instead
of only 2 ms. It allows comparing of waveforms before and after
design changes.
5
Warp Enterprise
Warp Enterprise provides even more features. It provides un-
limited timing simulation and source-level behavioral simula-
tion as well as a debugger. It has the ability to generate graph-
ical HDL blocks from HDL text. It can even generate
testbenches.
Warp is available for PC and UNIX platforms. Some features
are not available in the UNIX version. For further information
see the Warp for PC, Warp for UNIX, Warp Professional and
Warp Enterprise datasheets.
Third-Party Software
Although Warp is a complete CPLD development tool on its
own, it interfaces with nearly every third party EDA tool. All
major third-party software vendors provide support for the
MAX family of devices. To expedite this support, Cypress sup-
plies vendors with all pertinent architectural information as well
as design fitters for our products.
Programming
The Impulse3™ device programmers from Cypress will pro-
gram all Cypress PLDs, CPLDs, FPGAs, and PROMs. The
unit is a standalone programmer that connects to any
IBM-compatible PC via the printer port.
Third-Party Programmers
As with development software, Cypress strongly supports
third-party programmers. All major third-party programmers
support the MAX family.
Cross Reference
ALTERA
PREFIX EPM
PREFIX: EP
22V10–10C
22V10–10C
22V10–10C
22V10–10C
22V10–15C
22V10–15C
5032DC
5032DC–2
5032DC–15
5032DC–17
5032DC–20
5032DC–25
5032DM
5032DM–25
5032JC
5032JC–2
5032JC–15
5032JC–17
5032JC–20
CY7C340 EPLD Family
CYPRESS
PREFIX: CY
PREFIX: PALC
PALC22V10D–7C
PALC22V10D–10C
PAL22V10C–7C+
PAL22V10C–10C+
PALC22V10B–15C
PALC22V10D–15C
7C344–25WC
7C344–20WC
7C344–15WC
Call Factory
7C344–20WC
7C344–25WC
7C344–25WMB
7C344–25WMB
7C344–25HC
7C344–20HC
7C344–15HC
Call Factory
7C344–20HC