5962-9314401MZX Cypress Semiconductor Corp, 5962-9314401MZX Datasheet - Page 3

• Manufacturer Part Number: 5962-9314401MZX
• Manufacturer: Cypress Semiconductor Corp

Specifications of 5962-9314401MZX

• Memory Type: EPROM
• # Macrocells: 128
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Pin Count: 84
• Package Type: Windowed PGA
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
The Logic Array Block
The logic array block, shown in Figure 2, is the heart of the
MAX architecture. It consists of a macrocell array, expander
product term array, and an I/O block. The number of mac-
rocells, expanders, and I/O vary, depending upon the de-
vice used. Global feedback of all signals is provided within
a LAB, giving each functional block complete access to the
LAB resources. The LAB itself is fed by the programmable
interconnect array and dedicated input bus. The feedbacks
of the macrocells and I/O pins feed the PIA, providing ac-
cess to them through other LABs in the device. The mem-
bers of the CY7C340 family of EPLDs that have a single
LAB use a global bus, so a PIA is not needed (see Figure 3).
The MAX Macrocell
Traditionally, PLDs have been divided into either PLA (pro-
grammable AND, programmable OR), or PAL® (programma-
ble AND, fixed OR) architectures. PLDs of the latter type
provide faster input-to-output delays, but can be inefficient
due to fixed allocation of product terms. Statistical analysis
of PLD logic designs has shown that 70% of all logic func-
tions (per macrocell) require three product terms or less.
The macrocell structure of MAX has been optimized to handle
variable product term requirements. As shown in Figure 4,
each macrocell consists of a product term array and a con-
figurable register. In the macrocell, combinatorial logic is
implemented with three product terms ORed together,
which then feeds an XOR gate. The second input to the
XOR gate is also controlled by a product term, providing
the ability to control active HIGH or active LOW logic and
to implement T- and JK-type flip-flops.
I
N
P
U
T
S
PROGRAMMABLE
INTERCONNECT
P
I
A
Figure 2. Typical LAB Block Diagram
ARRAY
EXPANDER
PRODUCT
MACROCELL
ARRAY
TERM
ARRAY
BLOCK
I/O
C340–2
PINS
I/O
3
If more product terms are required to implement a given func-
tion, they may be added to the macrocell from the expander
product term array. These additional product terms may be
added to any macrocell, allowing the designer to build gate-in-
tensive logic, such as address decoders, adders, comparators,
and complex state machines, without using extra macrocells.
The register within the macrocell may be programmed for ei-
ther D, T, JK, or RS operation. It may alternately be configured
as a flow-through latch for minimum input-to-output delays, or
bypassed entirely for purely combinatorial logic. In addition,
each register supports both asynchronous preset and clear,
allowing asynchronous loading of counters of shift registers,
as found in many standard TTL functions. These registers may
be clocked with a synchronous system clock, or clocked inde-
pendently from the logic array.
Expander Product Terms
The expander product terms, as shown in Figure 5, are fed by
the dedicated input bus, the programmable interconnect ar-
ray, the macrocell feedback, the expanders themselves,
and the I/O pin feedbacks. The outputs of the expanders
then go to each and every product term in the macrocell
array. This allows expanders to be “shared” by the product
terms in the logic array block. One expander may feed all
macrocells in the LAB, or even multiple product terms in the
same macrocell. Since these expanders feed the second-
ary product terms (preset, clear, clock, and output enable)
of each macrocell, complex logic functions may be imple-
mented without utilizing another macrocell. Likewise, ex-
panders may feed and be shared by other expanders, to
implement complex multilevel logic and input latches.
I
N
P
U
T
S
Figure 3. 7C344 LAB Block Diagram
EXPANDER
PRODUCT
MACROCELL
ARRAY
TERM
CY7C340 EPLD Family
ARRAY
BLOCK
I/O
C340–3
PINS
I/O