MT4C4M4E8DJ-5 Micron Technology Inc, MT4C4M4E8DJ-5 Datasheet
MT4C4M4E8DJ-5
Specifications of MT4C4M4E8DJ-5
Available stocks
Related parts for MT4C4M4E8DJ-5
MT4C4M4E8DJ-5 Summary of contents
Page 1
... Refresh Rates Standard Refresh Self Refresh (128ms period) NOTE: 1. The 4 Meg x 4 EDO DRAM base number differentiates the offerings in one place - MT4LC4M4E8. The fifth field distinguishes various options: E8 designates a 2K refresh and E9 designates a 4K refresh for EDO DRAMs. 2. The “#” symbol indicates signal is active LOW. ...
Page 2
... The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#. The 4 Meg x 4 DRAM must be refreshed periodically in order to retain stored data. PAGE ACCESS Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row- address-defined page boundary ...
Page 3
... RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh se- quence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence, all rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation ...
Page 4
... REFRESH A7 COUNTER A10 ROW- A11 ADDRESS 12 BUFFERS (12) NO. 1 CLOCK RAS# GENERATOR 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/ 2,048 2,048 2,048 11 2,048 2,048 10 4,096 12 4,096 4,096 Micron Technology, Inc., reserves the right to change products or specifications without notice MEG x 4 EDO DRAM ...
Page 5
... V ≤ V OUT OUT DQ is disabled and in High-Z state 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 *Stresses greater than those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. ................. -1V to +4.6V This is a stress rating only, and functional operation of the ...
Page 6
... IN REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with t RAS# ≥ RASS (MIN) and CAS# held LOW; WE 0.2V; A0-A11, OE# and 0.2V (D may be left open Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 SYMBOL 0.2V 0.2V [MIN]) , ...
Page 7
... Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 SYMBOL SYMBOL MIN ...
Page 8
... WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 -5 SYMBOL MIN MAX MIN ...
Page 9
... CP. 16. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 17. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not permis- sible and should not be attempted. Additionally, WE# must be pulsed during CAS# HIGH time in order to place I/O buffers in High-Z ...
Page 10
... CLZ 0 t CRP 5 t CSH NOTE: 1. OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 READ CYCLE RAS t CSH t RSH t RCD t CAS RAD t RAH t ASC t CAH t ACH COLUMN t RCS RAC t CAC ...
Page 11
... CAH 8 t CAS 8 10,000 t CRP 5 t CSH 38 t CWL RAD 9 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 EARLY WRITE CYCLE RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t CWL t RWL t WCR t WCS t WCH VALID DATA -6 MIN ...
Page 12
... CAS 8 10,000 t CLZ 0 t CRP 5 t CSH 38 t CWD 28 t CWL Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 READ-WRITE CYCLE t RWC t RAS t CSH t RSH t RCD t CAS RAD t ASC t CAH t RAH COLUMN t RWD t RCS t CWD t AWD RAC t CAC t CLZ OPEN t OE ...
Page 13
... CAS 8 10,000 t CLZ 0 t COH CPA 28 t CRP 5 t CSH Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 EDO-PAGE-MODE READ CYCLE t RASP RCD t CAS ACH t ACH t ASC t CAH t ASC COLUMN COLUMN t RCS RAC t CAC t CLZ VALID DATA OES -6 MIN MAX UNITS ...
Page 14
... CAH 8 t CAS 8 10,000 CRP 5 t CSH 38 t CWL Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 EDO-PAGE-MODE EARLY WRITE CYCLE t RASP RCD t CAS ACH t ASC t CAH t ASC COLUMN COLUMN t CWL t WCS t WCH t WCS WCR VALID DATA VALID DATA -6 MIN ...
Page 15
... CPA 28 t CRP 5 t CSH 38 t CWD 28 t CWL NOTE for LATE WRITE cycles only. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 EDO-PAGE-MODE READ-WRITE CYCLE t RASP t CSH RCD t CAS ASC t CAH t ASC COLUMN COLUMN t RWD t RCS t CWL AWD t CWD CPA ...
Page 16
... CAH 8 t CAS 8 10,000 t COH CPA 28 t CRP 5 t CSH Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 (Pseudo READ-MODIFY-WRITE) t RASP t CSH CAS t CAS ASC t CAH t ASC t CAH COLUMN (A) COLUMN (B) t RCS CPA t RAC t CAC t COH VALID DATA ( MIN MAX ...
Page 17
... ASC 0 t ASR 0 t CAC 13 t CAH 8 t CAS 8 10,000 t CLZ CRP 5 t CSH 38 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 READ CYCLE (With WE#-controlled disable) t RCD RAD t RAH t ASC ROW COLUMN t RCS OPEN -6 MIN MAX UNITS SYMBOL RAC ...
Page 18
... CRP 5 t CSR 5 t RAH 9 NOTE: 1. End of first CBR REFRESH cycle. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) t RAS t RAH ROW OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) t RAS ...
Page 19
... ASR 0 t CAC 13 t CAH 8 t CHR 8 t CLZ 0 t CRP Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW) t RAS t RCD t RSH RAD t ASC t CAH COLUMN RAC t CAC t CLZ OPEN ORD -6 MIN MAX UNITS SYMBOL ...
Page 20
... RASS 100 NOTE: 1. Once RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode Once RPS is satisfied, a complete burst of all rows should be executed. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) ...
Page 21
... SEATING PLANE 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 24/26-PIN PLASTIC SOJ (300 mil) DA-1 .679 (17.25) ...
Page 22
... TYP 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 4 Meg x 4 EDO DRAM D47.p65 – Rev. 6/98 24/26-PIN PLASTIC TSOP (300 mil) DB-1 .037 (0.95) ...