PA28F016SC-95 Intel, PA28F016SC-95 Datasheet - Page 16

• Manufacturer Part Number: PA28F016SC-95
• Manufacturer: Intel

Specifications of PA28F016SC-95

• Density: 16Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
NOTES:
1. Bus operations are defined in Table 3.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Table 7 for a description of the status register bits.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
5. If the block is locked, RP# must be at V
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at V
8. If the master lock-bit is set, RP# must be at V
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
16
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Program
Block Erase and Program
Suspend
Block Erase and Program
Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
codes. See Section 4.2 for read identifier code data.
program to a locked block while RP# is V
master lock-bit is not set, a block lock-bit can be set while RP# is V
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V
Command
Bus Cycles
Req’d.
Table 4. Command Definitions
HH
1
2
1
2
2
1
2
2
2
1
IH
2
to enable block erase or program operations. Attempts to issue a block erase or
will fail.
HH
HH
to set a block lock-bit. RP# must be at V
to clear block lock-bits. The clear block lock-bits operation simultaneously
Notes
5,6
4
5
5
7
7
8
5
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
IH
(1)
.
Addr
BA
PA
BA
X
X
X
X
X
X
X
X
(9)
(2)
Data
FFH
D0H
90H
70H
50H
20H
40H
10H
B0H
60H
60H
60H
or
(3)
HH
to set the master lock-bit. If the
Oper
PRELIMINARY
Read
Read
Write
Write
Write
Write
Write
Second Bus Cycle
(1)
Addr
BA
PA
BA
IA
X
X
X
(2)
Data
SRD
D0H
F1H
D0H
01H
PD
ID
(3)
IH
.