PA28F016SC-95 Intel, PA28F016SC-95 Datasheet
PA28F016SC-95
Specifications of PA28F016SC-95
Related parts for PA28F016SC-95
PA28F016SC-95 Summary of contents
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... V block locking. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 m ETOX™ V process technology. They come in industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged 44-lead PSOP ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 1.0 INTRODUCTION .............................................5 1.1 New Features...............................................5 1.2 Product Overview.........................................5 1.3 Pinout and Pin Description ...........................6 2.0 PRINCIPLES OF OPERATION .....................12 2.1 Data Protection ..........................................13 3.0 BUS OPERATION .........................................13 3.1 Read ..........................................................13 3.2 Output Disable ...........................................13 3.3 Standby......................................................13 3.4 Deep Power-Down .....................................13 3.5 Read Identifier Codes Operation ................14 3 ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY REVISION HISTORY Number -001 Original version -002 Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program. Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead PSOP Ext. Temp. 44-Lead PSOP. ...
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... Section 8.0. 1.1 New Features The byte-wide SmartVoltage FlashFile memory family maintains backwards-compatibility Intel’s 28F008SA and 28F008SA-L. enhancements include: SmartVoltage Technology Enhanced Suspend Capabilities In-System Block Locking They share a compatible status register, software commands, and pinouts ...
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... program CC PP suspend operation permits system software to read data or execute code from any other flash memory array location. To protect programmed data, each block can be locked. This block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. The ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 4-Mbit Input 8-Mbit Decoder Buffer 16-Mbit Address X Latch Decoder Address Counter Figure 1. Block Diagram Table 2. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations Addresses are internally latched during a write cycle. ...
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... SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device CC for optimized read performance. Do not float any power pins. SmartVoltage Flash With all write attempts to the flash memory are inhibited. Device CC LKO operations at invalid V results and should not be attempted. Block erase, program, and lock-bit configuration operations with V GND SUPPLY GROUND: Do not float any ground pins ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY CE# STANDARD PINOUT CE# CE RP# RP# RP Figure 2. TSOP 40-Lead Pinout PRELIMINARY 28F016SC 28F008SC 28F004SC RY/BY 40-LEAD TSOP TOP VIEW GND 29 GND WE# WE# WE# OE# OE# OE# RY/BY# RY/BY GND GND GND GND ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Figure 3. PSOP 44-Lead Pinout 10 PRELIMINARY ...
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... Note that the signals are mirror images of bottom view. NOTES: 1. Figures are not drawn to scale. 2. Address A is not included in the 28F008SC More information on µBGA* packages is available by contacting your Intel/Distribution sales office. Figure 4. µBGA* CSP 40-Ball Pinout (28F008SC and 28F016SC) PRELIMINARY RP# ...
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... Read Array command. Block erase suspend allows system software to suspend a block erase to read or write data from any other block. Program suspend allows system software to suspend a program to read data from any other flash memory array location. 12 1FFFFF 64-Kbyte Block 1F0000 ...
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... CPU initialization may not occur because the flash IH memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 1FFFFF Block 31 Reserved for Future Implementation 1F0002 Block 31 Lock Configuration Reserved for Future Implementation 1F0000 (Blocks 16 through 30) 0FFFFF Block 15 Reserved for Future Implementation Block 15 Lock Configuration 0F0002 Reserved for Future Implementation 0F0000 (Blocks 8 through 14) ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Table 3. Bus Operations Mode Notes RP# Read 1,2 Output Disable Standby Deep Power-Down Read Identifier Codes Write 3,6 NOTES: 1. Refer to DC Characteristics . When PPLK 2. X can for control and address input pins and voltages. PPH1/2/3 3. RY/BY when the WSM is executing internal block erase, program, or lock-bit configuration algorithms ...
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... If the master lock-bit is set, RP# must clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 16 (9) ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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... The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written to the flash memory, the WSM will continue the program process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 4.10 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Table 7. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block Erase Loop No 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write 40H, Address Write Byte Data and Address Read Status Register Suspend Program Loop No 0 Suspend SR.7 = Program Yes 1 Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program ? Program Read Array No Loop Data Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data Figure 9. Block Erase Suspend/Resume Flowchart ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write B0H Read Status Register 0 SR Program Completed SR Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array Data Figure 10. Program Suspend/Resume Flowchart PRELIMINARY Bus Command Comments Operation ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error Device Protect Error SR ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error Device Protect Error SR. Command Sequence SR ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 5.0 DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections: CE#, OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation. b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 5.7 V Program and Erase PP Voltages on Sub-0.4µ SC Memory Family Intel's SmartVoltage FlashFile™ memory family provides in-system program/erase at 3 well as faster factory program/erase Future sub-0.4µ lithography SmartVoltage FlashFile memory products will also include a backward- compatible 12 V programming feature ...
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... NOTICE: This datasheet contains information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute (1) Maximum Ratings” ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 6.4 DC Characteristics—Commercial Temperature 2.7V V Parameter Sym Notes Typ Max Typ Max Typ Max Unit I Input Load Current Output Leakage Current Standby Current 1,3,6 20 CCS CC 0 Deep Power- 1 CCD CC Down Current I V Read Current 1,5,6 ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 6.4 DC Characteristics—Commercial Temperature 2 Sym Parameter Notes Min Max Min Max Min Max Unit V Input Low Voltage 7 –0.5 0.8 –0.5 0.8 –0.5 0 Input High Voltage 7 2 Output Low Voltage 3 Output High Voltage (TTL) 3,7 2.4 ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 2.7 INPUT 1.35 0.0 AC test inputs are driven at 2.7 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V. Input rise and fall times (10% to 90%) <10 ns. Figure 13. Transient Input/Output Reference Waveform for V 3 ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY V IH RY/BY# ( RP# ( Figure 17. AC Waveform for Reset Operation Table 8. Reset Specifications # Sym Parameter P1 t RP# Pulse Low Time (If RP# is tied to V PLPH this specification is not applicable RP# Low to Reset during Block Erase, PLRH Program, or Lock-Bit Configuration NOTES: 1 ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 6.5 AC Characteristics—Read-Only Operations T = 0°C to +70° ± Versions ( ± 10 3.3 V ± 0 2 Sym Parameter Notes Min Max Min Max Min Max Min Max Min Max R1 t Read Cycle 4, 8 Mbit AVAV Time ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ7 RP# ( Figure 18. AC Waveform for Read Operations 36 Device Data Address Selection Valid Address Stable R10 R6 Valid Output R7 PRELIMINARY R8 R9 High Z ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 6.6 AC Characteristics—Write Operations T = 0°C to +70°C A Versions # Sym Parameter RP# High Recovery to WE# (CE#) Going PHWL PHEL Low CE# (WE#) Setup to WE# (CE#) Going ELWL WLEL Low W3 t Write Pulse Width Data Setup to WE# (CE#) Going High DVWH ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY ADDRESSES [ CE# (WE#) [E(W OE# [ WE# (CE#) [W(E High Z DATA [D/ RY/BY# [ RP# [ PPH2 PPLK V IL NOTES power-up and standby Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read status register data. ...
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... BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 6.7 Block Erase, Program, and Lock-Bit Configuration Performance Commercial Temperature V = 3.3 V ± 0 0°C to +70° Sym Parameter Notes W16 t , Program Time 2 WHRH1 t EHRH1 Block Write Time 2 W16 t , Block Erase Time 2 WHRH2 t EHRH2 W16 t , Set Lock-Bit Time ...
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... Current NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 6.10 AC Characteristics—Read-Only Operations T = –40°C to +85° ± ...
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... Mbit Order Code by Density 4-Mbit 8-Mbit Commercial Temperature E28F004SC-85 E28F008SC-85 E28F016SC-95 E28F004SC-120 E28F008SC-120 E28F016SC-120 PA28F004SC-85 PA28F008SC-85 PA28F016SC-95 PA28F004SC-120 PA28F008SC-120 PA28F016SC-120 G28F008SC-120 G28F016SC-120 G28F008SC-150 G28F016SC-150 TE28F004SC-100 TE28F008SC-100 TE28F016SC-110 TB28F004SC-100 TB28F008SC-100 TB28F016SC-110 NOTE: 1. Valid access time for 16-Mbit byte-wide FlashFile memory. PRELIMINARY 5 ...
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... Models Sales Office NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. ...