TE28F800F3T95 Intel, TE28F800F3T95 Datasheet - Page 38

• Manufacturer Part Number: TE28F800F3T95
• Manufacturer: Intel

Specifications of TE28F800F3T95

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
8.5
32
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R1
R2
R3
R4
R5
R6
R7
R8
R9
#
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CH
CHCL
AVCH
VLCH
ELCH
CHQV
CHQX
CHAX
CHTL
AVVH
ELVH
AVQV
ELQV
VLQV
VLVH
VHVL
VHAX
APA
GLQV
PHQV
EHQZ
GHQZ
OH
EHEL
Symbol
(t
CL
)
AC Characteristics—Read-Only Operations
Automotive Temperature
NOTES:
1. See
2. Data bus voltage must be less than or equal to V
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is defined as t
5. OE# may be delayed up to t
6. ADV# tied to ground, t
measurements and maximum allowable input slew rate.
specifications.
satisfied first.
CLK Period
CLK High (Low) Time
CLK Fall (Rise) Time
Address Valid Setup to CLK
ADV# Low Setup to CLK
CE# Low Setup to CLK
CLK to Output Delay
Output Hold from CLK
Address Hold from CLK
CLK to WAIT# delay
Address Setup to ADV# High
CE# Low to ADV# High
Address to Output Delay
CE# Low to Output Delay
ADV# Low to Output Delay
ADV# Pulse Width Low
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
OE# Low to Output Delay
RST# High to Output Delay
CE# or OE# High to Output in
High Z, Whichever Occurs First
Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First
CE# High Pulse Width
Figure 11, “AC Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V” on page 31
Parameter
EHEL
(CE# High Pulse Width) must be held high for a minimum of 15 ns.
ELQV
–t
GLQV
Product
after the falling edge of CE# without impact on t
Notes
V
3
4
3
5
4
3
3
6
CC
CCQ
3.0 V— 3.6 V
Min
2.5
15
10
10
10
10
10
10
10
10
when a read operation is initiated to guarantee AC
3
3
0
0
CHAX
–80
Max
600
or t
17
19
80
80
80
25
40
23
5
VHAX
3.0 V— 3.6 V
, whichever timing specification is
Min
2.5
15
10
10
10
10
10
10
10
10
3
3
0
0
–95
Max
600
19
95
95
95
(1,2)
19
25
40
25
5
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
PRELIMINARY
.
for timing