TE28F800B5T90 Intel, TE28F800B5T90 Datasheet - Page 39

• Manufacturer Part Number: TE28F800B5T90
• Manufacturer: Intel

Specifications of TE28F800B5T90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

5.11
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
7. Time t
8. Sampled, but not 100% tested.
9. Write pulse width (t
10. Write pulse width high (t
W10 t
W11 t
W12 t
W13 t
W14 t
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
Characteristics—Read-Only Operations.
which includes verify operations.
successfully.
(whichever goes high first). Hence, t
(whichever goes low first). Hence, t
PRELIMINARY
#
PHBR
t
t
t
t
t
t
t
t
t
t
AC Characteristics—Write Operations—Automotive Temperature
AVAV
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
PHHWH
VPWH
QVPH
QVVL
PHBR
is required for successful locking of the boot block.
Sym
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
AVEH
EHAX
(t
VPEH
DVEH
EHWH
EHDX
PHHEH
WP
)
)
)
)
)
)
)
)
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
)
WPH
Write Cycle Time
RP# High Recovery to WE#
(CE#) Going Low
CE# (WE#) Setup to WE#
(CE#) Going Low
Write Pulse Width
Data Setup to WE# (CE#)
Going High
Address Setup to WE# (CE#)
Going High
CE# (WE#) Hold from WE#
(CE#) High
Data Hold from WE# (CE#)
High
Address Hold from WE# (CE#)
High
Write Pulse Width
High
RP# V
Going High
V
High
RP# V
V
Boot Block Lock Delay
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
PP
PP
Setup to WE# (CE#) Going
Hold from Valid SRD
WPH
HH
HH
WP
Parameter
Setup to WE# (CE#)
Hold from Valid SRD
= t
= t
WLWH
WHWL
IN
IN
. (Table 7)
. (Table 7)
= t
= t
ELEH
EHEL
V
CC
5%
HH
= t
= t
2,4 Mbit
WLEH
8 Mbit
or WP# should be held at V
WHEL
= 5 V
= t
= t
ELWH
EHWL
Speed
Note
6,8
5,8
6,8
5,8
7,8
9
4
3
4
3
.
.
28F200B5, 28F004/400B5, 28F800B5
Min
450
100
100
80
80
60
60
60
10
0
0
0
0
0
0
-80
IH
Max
100
until operation completes
Min
450
100
100
n/a
90
60
60
60
10
0
0
0
0
0
0
-90
Max
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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