TE28F800B5T90 Intel, TE28F800B5T90 Datasheet - Page 24

• Manufacturer Part Number: TE28F800B5T90
• Manufacturer: Intel

Specifications of TE28F800B5T90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

28F200B5, 28F004/400B5, 28F800B5
3.3
The boot block family architecture features a
hardware-lockable boot block so that the kernel
code for the system can be kept secure while the
parameter and main blocks are programmed and
erased independently as necessary. Only the boot
block can be locked independently from the other
blocks.
3.3.1
For complete write protection of all blocks in the
device, the V
is below V
result in a error in the status register.
3.3.2
When WP# = V
program or erase operation to the boot block will
result in an error in the status register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this
feature is overridden and the boot block unlocked
when RP# = V
3.3.3
Two methods can be used to unlock the boot block:
1. WP# = V
2. RP# = V
If both or either of these two conditions are met, the
boot
programmed or erased.
The Write Proctection Truth Table , Table 9, clearly
defines the write protection methods.
3.3.4
The 8-Mbit in the 44-PSOP package does not have
a WP# because no other pins were available for the
8-Mbit upgrade address. Thus, in this density-
package combination only, V
required to unlock the boot block and unlocking with
a logic-level signal is not possible. If this unlocking
24
block
Boot Block Locking
PPLK
V
PROTECTION
WP# = V
LOCKING
RP# = V
BLOCK UNLOCKING
NOTE FOR 8-MBIT 44-PSOP
PACKAGE
HH
PP
IH
PP
HH
will
, any program or erase operation will
= V
IL
voltage can be held low. When V
.
, the boot block is locked and any
IL
HH
IL
be
FOR COMPLETE
FOR BOOT BLOCK
OR WP# = V
unlocked
HH
(12 V) on RP# is
IH
and
FOR BOOT
can
be
PP
functionality is required, and 12 V is not available
in-system, please consider using the 48-TSOP
package, which has a WP# pin and can be
unlocked with a logic-level signal. All other density-
package combinations have WP# pins.
4.0
The following section discusses recommended
design considerations which can improve the
robustness of system designs using flash memory.
4.1
Intel flash components contain features designed to
reduce power requirements. The following sections
will detail how to take advantage of these features.
4.1.1
Asserting CE# to a logic-low level and RP# to a
logic-high level places the device in the active
mode. Refer to the DC Characteristics table for I
current values.
4.1.2
Automatic Power Savings (APS) provides low-
power operation in active mode. Power Reduction
Control (PRC) circuitry allows the device to put
itself into a low current state when not being
accessed. After data is read from the memory
array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical I
stays in this static state with outputs valid until a
new location is read.
V
V
V
V
V
V
PPLK
PPLK
PPLK
PPLK
PP
IL
Table 9. Write Protection Truth Table
DESIGN CONSIDERATIONS
CC
Power Consumption
ACTIVE POWER
AUTOMATIC POWER SAVINGS (APS)
current is less than 1 mA. The device
RP#
V
V
V
V
X
HH
IL
IH
IH
WP#
V
V
X
X
X
IL
IH
PRELIMINARY
All Blocks Locked
All Blocks Locked
(Reset)
All Blocks Unlocked
Boot Block Locked
All Blocks Unlocked
Write Protection
Provided
CCR