TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 33

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

6.6
T
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
A
W10 t
W11 t
W12 t
W13 t
W14 t
W15 t
W1
W2
W3
W4
W5
W6
W7
W8
W9
= 0 °C to +70 °C
PRELIMINARY
#
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics—Read-Only Operations .
A write operation can be initiated and terminated with either CE# or WE#.
Sampled, not 100% tested.
Refer to Table 3 for valid A
V
lock-bit configuration success (SR.1/3/4/5 = 0).
See Ordering Information for device speeds (valid operational combinations).
Write pulse width (t
(whichever goes high first). Hence, t
WE# pulse width requirement decreases to t
Write pulse width high (t
(whichever goes low last). Hence, t
PP
should be held at V
t
t
t
t
t
t
t
t
t
AC Characteristics— Write Operations
PHWL
ELWL
WP
DVWH
AVWH
WHEH
WHDX
WHAX
WPH
PHHWH
VPWH
WHGL
WHRL
QVPH
QVVL
Sym
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
AVEH
EHAX
(t
VPEH
EHGL
EHRL
DVEH
EHWH
EHDX
PHHEH
WP
)
)
)
)
)
)
)
)
)
)
) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
) RP# V
PPH1/2
WPH
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
Write Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
Write Pulse Width High
V
Write Recovery before Read
WE# (CE#) High to RY/BY# Going Low
RP# V
V
IN
PP
PP
) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
and D
(and if necessary RP# should be held at V
Versions
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY# High
HH
HH
WPH
IN
WP
Setup to WE# (CE#) Going High
Hold from Valid SRD, RY/BY# High
for block erase, program, or lock-bit configuration.
= t
= t
(4)
WLWH
WHWL
WP
- 20 ns.
= t
= t
ELEH
EHEL
Parameter
= t
= t
WLEH
WHEL
= t
= t
(1, 2)
ELWH
EHWL
. If CE# is driven low 10 ns before WE# going low,
.
—Commercial Temperature
HH
) until determination of block erase, program, or
28F004S5, 28F008S5, 28F016S5
5 V ± 10% V
5 V ± 5%,
Notes Min
3,5
3,5
3
7
7
4
4
8
3
3
CC
Valid for All
100
100
50
40
40
25
1
0
0
5
5
0
0
0
Speeds
Max
90
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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