TB28F004S5-100 Intel, TB28F004S5-100 Datasheet - Page 16

• Manufacturer Part Number: TB28F004S5-100
• Manufacturer: Intel

Specifications of TB28F004S5-100

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 512K
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F004S5, 28F008S5, 28F016S5
(the same V
block erase is suspended. RP# must also remain at
V
erase). Block erase cannot resume until program
operations initiated during block erase suspend
have completed.
4.8
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the program process starts, writing
the Program Suspend command requests that the
WSM suspend the program sequence at a
predetermined point in the algorithm. The device
continues to output status register data when read
after the Program Suspend command is written.
Polling status register bits SR.7 and SR.2 can
determine when the program operation has been
suspended (both will be set to “1”). RY/BY# will also
transition to V
program suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
program is suspended are Read Status Register
and Program Resume. After Program Resume
command is written to the flash memory, the WSM
will continue the program process. Status register
bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V
Resume
automatically outputs status register data when
read (see Figure 9). V
(the same V
program suspend mode. RP# must also remain at
V
4.9
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits and a
master lock-bit. The block lock-bits gate program
and erase operations while the master lock-bit
gates block-lock bit modification. With the master
lock-bit not set, individual block lock-bits can be set
using the Set Block Lock-Bit command. The Set
Master Lock-Bit command, in conjunction with
RP# = V
master lock-bit is set, subsequent setting of block
lock-bits requires both the Set Block Lock-Bit
command and V
16
IH
IH
or V
or V
HH
HH
Program Suspend Command
Set Block and Master Lock-Bit
Commands
HH
(the same RP# level used for program).
command
, sets the master lock-bit. After the
(the same RP# level used for block
PP
PP
OH
HH
level used for block erase) while
. Specification t
level used for program) while in
on the RP# pin. See Table 5 for
PP
is
OL
must remain at V
written,
. After the Program
WHRH1
the
defines the
device
PPH1/2
a summary of hardware and software write
protection options.
Set block lock-bit and master lock-bit are initiated
using two-cycle command sequence. The set block
or master lock-bit setup along with appropriate
block or device address is written followed by either
the set block lock-bit confirm (and an address within
the block to be locked) or the set master lock-bit
confirm (and any device address). The WSM then
controls the set lock-bit algorithm. After the
sequence is written, the device automatically
outputs status register data when read (see
Figure 10). The CPU can detect the completion of
the set lock-bit event by analyzing the RY/BY# pin
output or status register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block or Master Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to “1.” Also, reliable operations
occur only when V
the absence of this high voltage, lock-bit contents
are protected against alteration.
A successful set block lock-bit operation requires
that the master lock-bit be cleared or, if the master
lock-bit is set, that RP# = V
the master lock-bit set and RP# = V
will fail, and SR.1 and SR.4 will be set to “1.” A
successful set master lock-bit operation requires
that RP# = V
the operation will fail, and SR.1 and SR.4 will be set
to “1.” Set block and master lock-bit operations with
V
should not be attempted.
4.10
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits
requires both the Clear Block Lock-Bits command
and V
summary of hardware and software write protection
options.
IH
< RP# < V
HH
Clear Block Lock-Bits
Command
on the RP# pin. See Table 5 for a
HH
. If it is attempted with RP# = V
HH
CC
produce spurious results and
= V
CC1/2
PRELIMINARY
HH
. If it is attempted with
and V
IH
PP
, the operation
= V
PPH1/2
. In
IH
,