TB28F400BVT80 Intel, TB28F400BVT80 Datasheet - Page 39

• Manufacturer Part Number: TB28F400BVT80
• Manufacturer: Intel

Specifications of TB28F400BVT80

• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 85C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 70mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
3. Refer to command definition table for valid A
4. Refer to command definition table for valid D
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
7. Time t
8. Sampled, but not 100% tested.
9. See Test Configuration (Figure 14), 3.3 V Standard Test component values.
10. See Test Configuration (Figure 14), 5 V High-Speed Test component values.
11. See Test Configuration (Figure 14), 5 V Standard Test component values.
NOTES:
1. V
2. Write Program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
Characteristics during read mode.
which includes verify and margining operations.
successfully.
SEE NEW DESIGN RECOMMENDATIONS
CC
Power-Up and Standby.
PHBR
ADDRESSES (A)
is required for successful locking of the boot block.
CE# (E)
OE# (G)
WE# (W)
DATA (D/Q)
RP# (P)
WP#
V
Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)
PP
6.5V
(V)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
HH
PPH
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
PPH
IL
PPLK
t
ELWL
1
2
1
High Z
t
PHWL
t
A
AVAV
IN
2
D
IN
t
WHWL
IN
IN
t
. (Table 7)
. (Table 7)
WHEH
t
t
t
WLWH
DVWH
WHDX
t
AVWH
A
3
IN
D
HH
IN
t
t
PHHWH
VPWH
or WP# should be held at V
t
t
4-MBIT SmartVoltage BOOT BLOCK FAMILY
WHAX
WHQV1,2,3,4
4
5
Valid
SRD
t
t
QVVL
QVPH
IH
until operation completes
6
D
IN
0530_17
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