LH28F016SCR-L95 Sharp Electronics, LH28F016SCR-L95 Datasheet - Page 18

• Manufacturer Part Number: LH28F016SCR-L95
• Manufacturer: Sharp Electronics

Specifications of LH28F016SCR-L95

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.10 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With the master
lock-bit not set, block lock-bits can be cleared using
only the Clear Block Lock-Bits command. If the
master lock-bit is set, clearing block lock-bits requires
both the Clear Block Lock-Bits command and V
the RP# pin. See Table 6 for a summary of hardware
and software write protection options.
Clear block lock-bits operation is executed by a
two-cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 10). The CPU can detect
completion of the clear block lock-bits event by
analyzing the RY/BY# Pin output or status register bit
SR.7.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
Block Erase or
Byte Write
Set Block
Lock-Bit
Set Master
Lock-Bit
Clear Block
Lock-Bits
Operation
Lock-Bit
Master
X
X
0
1
0
1
Lock-Bit
Block
X
X
X
X
X
0
1
Table 6. Write Protection Alternatives
V
V
V
IH
IH
IH
RP#
V
V
V
V
V
V
V
V
or V
or V
or V
HH
HH
HH
HH
HH
IH
IH
IH
IH
LHF16CZN
on
HH
HH
HH
Block Erase and Byte Write Enabled
Block is Locked. Block Erase and Byte Write Disabled
Block Lock-Bit Override. Block Erase and Byte Write
Enabled
Set Block Lock-Bit Enabled
Master Lock-Bit is Set. Set Block Lock-Bit Disabled
Master Lock-Bit Override. Set Block Lock-Bit Enabled
Set Master Lock-Bit Disabled
Set Master Lock-Bit Enabled
Clear Block Lock-Bits Enabled
Master Lock-Bit is Set. Clear Block Lock-Bits Disabled
Master Lock-Bit Override. Clear Block Lock-Bits
Enabled
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to "1". Also, a reliable clear
block lock-bits operation can only occur when
V
lock-bits operation is attempted while V
SR.3 and SR.5 will be set to "1". In the absence of
this high voltage, the block lock-bits content are
protected against alteration. A successful clear block
lock-bits operation requires that the master lock-bit is
not set or, if the master lock-bit is set, that RP#=V
If it is attempted with the master lock-bit set and
RP#=V
operation will fail. A clear block lock-bits operation
with V
should not be attempted.
If a clear block lock-bits operation is aborted due to
V
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values. Once the master lock-bit is set, it
cannot be cleared.
CC
PP
=V
or V
CC2/3/4
IH
IH
, SR.1 and SR.5 will be set to "1" and the
<RP#<V
CC
transitioning out of valid range or RP#
and V
HH
Effect
PP
produce spurious results and
=V
PPH1/2/3
. If a clear block
PP
Rev. 1.2
≤V
PPLK
HH
15
,
.